From patchwork Tue Sep 17 10:45:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 275425 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 609772C00E0 for ; Tue, 17 Sep 2013 20:51:58 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8E4314A0BA; Tue, 17 Sep 2013 12:51:49 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9MWQ7saEq77s; Tue, 17 Sep 2013 12:51:49 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8EB3C4A0BD; Tue, 17 Sep 2013 12:51:42 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 914934A09D for ; Tue, 17 Sep 2013 12:51:30 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Hc3atL8yYKMJ for ; Tue, 17 Sep 2013 12:51:25 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mout.perfora.net (mout.perfora.net [74.208.4.195]) by theia.denx.de (Postfix) with ESMTPS id 995794A0A2 for ; Tue, 17 Sep 2013 12:51:25 +0200 (CEST) Received: from sumo-PORTEGE-R700.toradex.int (46-140-72-82.static.cablecom.ch [46.140.72.82]) by mrelay.perfora.net (node=mrus0) with ESMTP (Nemesis) id 0Mdb08-1VY2vF0TnA-00PMYq; Tue, 17 Sep 2013 06:46:21 -0400 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Tue, 17 Sep 2013 12:45:07 +0200 Message-Id: <6f62ebb5fef03f50fec97e90cc2df2879ed68442.1379414181.git.marcel@ziswiler.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: X-Provags-ID: V02:K0:WxXrlh9fcucLoM50ja4P/8bxRG/krvQ64/eVovQl8l0 cZx5/MH1cvFk90Qk0w1PcjGlm+n3WjyWEWAV/LlBikOZSi8HlZ /59wy1nlELtpPBBGuefpgbaLOSQQ03g31EV7VqVDZCAUaJYVs9 yWcrPwFDBM8WUIG6HdvYWnsQGLLMBalgEZoHmwJR7SB5pru9ul NCTVEaj0SRzOoaVQwWUmQjnehxuc3tLV3i0jDSDIt0Gs4ZgHaj q+grc5DODJeUaSQ34PBGjghL9bPWncx2GS0FM1PQ+3wdVjSity xq8/rKdwBTfqDCx85ce5Za6jbO3Ls1QORw1/qt24LRJ0VcDpIK vz7C06KEUcY2vE7Esa2YIHKTlkEhPwHbysNA3bN6J1fLXduOPm cR468HYbAbsmcLVpuhMUZSE2OWsHvMJrsWirxeut0Xy8yNUmt0 g5e2Fg1ml+hsBwqYvfMO5Xoi5Aw== Cc: Marcel Ziswiler Subject: [U-Boot] [PATCH 02/10] arm: vf610: clean-up anadig register struct X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Re-number all the resv reserved fields. Signed-off-by: Marcel Ziswiler --- arch/arm/include/asm/arch-vf610/crm_regs.h | 54 ++++++++++++++-------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 57a0242..d5c9387 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -55,59 +55,59 @@ struct ccm_reg { /* Analog components control digital interface (ANADIG) */ struct anadig_reg { - u32 resvA[4]; + u32 resv0[4]; u32 pll3_ctrl; - u32 resv0[3]; - u32 pll7_ctrl; u32 resv1[3]; - u32 pll2_ctrl; + u32 pll7_ctrl; u32 resv2[3]; - u32 pll2_ss; + u32 pll2_ctrl; u32 resv3[3]; - u32 pll2_num; + u32 pll2_ss; u32 resv4[3]; - u32 pll2_denom; + u32 pll2_num; u32 resv5[3]; - u32 pll4_ctrl; + u32 pll2_denom; u32 resv6[3]; - u32 pll4_num; + u32 pll4_ctrl; u32 resv7[3]; + u32 pll4_num; + u32 resv8[3]; u32 pll4_denom; - u32 resvB[3]; + u32 resv9[3]; u32 pll6_ctrl; - u32 resv8[3]; + u32 resv10[3]; u32 pll6_num; - u32 resv9[3]; + u32 resv11[3]; u32 pll6_denom; - u32 resv10[7]; + u32 resv12[7]; u32 pll5_ctrl; - u32 resv11[3]; + u32 resv13[3]; u32 pll3_pfd; - u32 resv12[3]; + u32 resv14[3]; u32 pll2_pfd; - u32 resv13[3]; + u32 resv15[3]; u32 reg_1p1; - u32 resv14[3]; + u32 resv16[3]; u32 reg_3p0; - u32 resv15[3]; + u32 resv17[3]; u32 reg_2p5; - u32 resv16[7]; + u32 resv18[7]; u32 ana_misc0; - u32 resv17[3]; + u32 resv19[3]; u32 ana_misc1; - u32 resv18[63]; + u32 resv20[63]; u32 anadig_digprog; - u32 resv19[3]; + u32 resv21[3]; u32 pll1_ctrl; - u32 resv20[3]; + u32 resv22[3]; u32 pll1_ss; - u32 resv21[3]; + u32 resv23[3]; u32 pll1_num; - u32 resv22[3]; + u32 resv24[3]; u32 pll1_denom; - u32 resv23[3]; + u32 resv25[3]; u32 pll1_pdf; - u32 resv24[3]; + u32 resv26[3]; u32 pll_lock; }; #endif