Patchwork Add a few more mpc5200 PSC defines

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Submitter Jon Smirl
Date May 22, 2009, 3:25 p.m.
Message ID <20090522152510.20037.26911.stgit@terra>
Download mbox | patch
Permalink /patch/27531/
State Not Applicable
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Comments

Jon Smirl - May 22, 2009, 3:25 p.m.
Add a few more mpc5200 PSC defines. More bit fields defines for mpc5200 PSC registers

Signed-off-by: Jon Smirl <jonsmirl@gmail.com>
---
 arch/powerpc/include/asm/mpc52xx_psc.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)
Jon Smirl - May 22, 2009, 4:06 p.m.
On Fri, May 22, 2009 at 11:33 AM, Grant Likely
<grant.likely@secretlab.ca> wrote:
> On Fri, May 22, 2009 at 9:25 AM, Jon Smirl <jonsmirl@gmail.com> wrote:
>> Add a few more mpc5200 PSC defines. More bit fields defines for mpc5200 PSC registers
>>
>> Signed-off-by: Jon Smirl <jonsmirl@gmail.com>
>
> Thanks Jon,
>
> What are you adding these defines for (so I can add it to the commit log)?

AC97 support

>
> g.
>
>> ---
>>  arch/powerpc/include/asm/mpc52xx_psc.h |   11 +++++++++++
>>  1 files changed, 11 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h
>> index a218da6..fb84120 100644
>> --- a/arch/powerpc/include/asm/mpc52xx_psc.h
>> +++ b/arch/powerpc/include/asm/mpc52xx_psc.h
>> @@ -28,6 +28,10 @@
>>  #define MPC52xx_PSC_MAXNUM     6
>>
>>  /* Programmable Serial Controller (PSC) status register bits */
>> +#define MPC52xx_PSC_SR_UNEX_RX 0x0001
>> +#define MPC52xx_PSC_SR_DATA_VAL        0x0002
>> +#define MPC52xx_PSC_SR_DATA_OVR        0x0004
>> +#define MPC52xx_PSC_SR_CMDSEND 0x0008
>>  #define MPC52xx_PSC_SR_CDE     0x0080
>>  #define MPC52xx_PSC_SR_RXRDY   0x0100
>>  #define MPC52xx_PSC_SR_RXFULL  0x0200
>> @@ -61,6 +65,12 @@
>>  #define MPC52xx_PSC_RXTX_FIFO_EMPTY    0x0001
>>
>>  /* PSC interrupt status/mask bits */
>> +#define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001
>> +#define MPC52xx_PSC_IMR_DATA_VALID     0x0002
>> +#define MPC52xx_PSC_IMR_DATA_OVR       0x0004
>> +#define MPC52xx_PSC_IMR_CMD_SEND       0x0008
>> +#define MPC52xx_PSC_IMR_ERROR          0x0040
>> +#define MPC52xx_PSC_IMR_DEOF           0x0080
>>  #define MPC52xx_PSC_IMR_TXRDY          0x0100
>>  #define MPC52xx_PSC_IMR_RXRDY          0x0200
>>  #define MPC52xx_PSC_IMR_DB             0x0400
>> @@ -117,6 +127,7 @@
>>  #define MPC52xx_PSC_SICR_SIM_FIR               (0x6 << 24)
>>  #define MPC52xx_PSC_SICR_SIM_CODEC_24          (0x7 << 24)
>>  #define MPC52xx_PSC_SICR_SIM_CODEC_32          (0xf << 24)
>> +#define MPC52xx_PSC_SICR_AWR                   (1 << 30)
>>  #define MPC52xx_PSC_SICR_GENCLK                        (1 << 23)
>>  #define MPC52xx_PSC_SICR_I2S                   (1 << 22)
>>  #define MPC52xx_PSC_SICR_CLKPOL                        (1 << 21)
>>
>>
>
>
>
> --
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
>

Patch

diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h
index a218da6..fb84120 100644
--- a/arch/powerpc/include/asm/mpc52xx_psc.h
+++ b/arch/powerpc/include/asm/mpc52xx_psc.h
@@ -28,6 +28,10 @@ 
 #define MPC52xx_PSC_MAXNUM	6
 
 /* Programmable Serial Controller (PSC) status register bits */
+#define MPC52xx_PSC_SR_UNEX_RX	0x0001
+#define MPC52xx_PSC_SR_DATA_VAL	0x0002
+#define MPC52xx_PSC_SR_DATA_OVR	0x0004
+#define MPC52xx_PSC_SR_CMDSEND	0x0008
 #define MPC52xx_PSC_SR_CDE	0x0080
 #define MPC52xx_PSC_SR_RXRDY	0x0100
 #define MPC52xx_PSC_SR_RXFULL	0x0200
@@ -61,6 +65,12 @@ 
 #define MPC52xx_PSC_RXTX_FIFO_EMPTY	0x0001
 
 /* PSC interrupt status/mask bits */
+#define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001
+#define MPC52xx_PSC_IMR_DATA_VALID	0x0002
+#define MPC52xx_PSC_IMR_DATA_OVR	0x0004
+#define MPC52xx_PSC_IMR_CMD_SEND	0x0008
+#define MPC52xx_PSC_IMR_ERROR		0x0040
+#define MPC52xx_PSC_IMR_DEOF		0x0080
 #define MPC52xx_PSC_IMR_TXRDY		0x0100
 #define MPC52xx_PSC_IMR_RXRDY		0x0200
 #define MPC52xx_PSC_IMR_DB		0x0400
@@ -117,6 +127,7 @@ 
 #define MPC52xx_PSC_SICR_SIM_FIR		(0x6 << 24)
 #define MPC52xx_PSC_SICR_SIM_CODEC_24		(0x7 << 24)
 #define MPC52xx_PSC_SICR_SIM_CODEC_32		(0xf << 24)
+#define MPC52xx_PSC_SICR_AWR			(1 << 30)
 #define MPC52xx_PSC_SICR_GENCLK			(1 << 23)
 #define MPC52xx_PSC_SICR_I2S			(1 << 22)
 #define MPC52xx_PSC_SICR_CLKPOL			(1 << 21)