From patchwork Sat Sep 14 21:54:43 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 274975 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4AD972C0155 for ; Sun, 15 Sep 2013 08:09:42 +1000 (EST) Received: from localhost ([::1]:54773 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKy28-0005Ch-9h for incoming@patchwork.ozlabs.org; Sat, 14 Sep 2013 18:09:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34774) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKxoa-0001rM-FT for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VKxoU-0004AF-Il for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:40 -0400 Received: from mail-pd0-x231.google.com ([2607:f8b0:400e:c02::231]:40408) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKxoU-0004A5-2Z for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:34 -0400 Received: by mail-pd0-f177.google.com with SMTP id y10so2618401pdj.36 for ; Sat, 14 Sep 2013 14:55:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=V7iq0RbygqTxWi64QrhABawM9MXcd/p7EZV3NJvUlGc=; b=tbQMe4s9sCcjp+vq9Ht+Y6gcvaMr1KjkYdKpEgUF0Yxg4IxWMoSyLJpahv54gyG5Z/ B1VbOhLXhKlfm7908Jb8FEMjIZdnCNOJ7xaonTudAYFFb1wPqnbLPI/FbGpWAGUyCvyL a+jT5qLIQXc2kkW83JzDJgZX2AM9wIXGavGPlYEtuo4EJlZ94aeEHjraF8qzWSguSHVD 4XF5Ge7fDYbyk3oM9Pfn0Bk3UUbgftT451smn+qaG0fRj4qJ2YIwOkj2lqeP3yJyhtYn goKaU+dHXeT+IN4jQoM9m7MdpDNyojWB3PPvKRJ43Rawm6tR1Jamf0/hmfq62kMZWJMY FZrQ== X-Received: by 10.68.252.33 with SMTP id zp1mr20811042pbc.95.1379195733112; Sat, 14 Sep 2013 14:55:33 -0700 (PDT) Received: from pebble.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id gg10sm20458962pbc.46.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sat, 14 Sep 2013 14:55:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 14 Sep 2013 14:54:43 -0700 Message-Id: <1379195690-6509-27-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1379195690-6509-1-git-send-email-rth@twiddle.net> References: <1379195690-6509-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::231 Cc: peter.maydell@linaro.org, claudio.fontana@gmail.com Subject: [Qemu-devel] [PATCH v4 26/33] tcg-aarch64: Avoid add with zero in tlb load X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Some guest env are small enough to reach the tlb with only a 12-bit addition. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 5691cc3..1905271 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -1136,46 +1136,58 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, int opc, slow path for the failure case, which will be patched later when finalizing the slow path. Generated code returns the host addend in X1, clobbers X0,X2,X3,TMP. */ -static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, - int s_bits, uint8_t **label_ptr, int mem_index, int is_read) +static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, int s_bits, + uint8_t **label_ptr, int mem_index, int is_read) { TCGReg base = TCG_AREG0; int tlb_offset = is_read ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write); + /* Extract the TLB index from the address into X0. X0 = addr_reg */ tcg_out_ubfm(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, addr_reg, TARGET_PAGE_BITS, TARGET_PAGE_BITS + CPU_TLB_BITS); + /* Store the page mask part of the address and the low s_bits into X3. Later this allows checking for equality and alignment at the same time. X3 = addr_reg & (PAGE_MASK | ((1 << s_bits) - 1)) */ tcg_fmt_Rdn_limm(s, INSN_ANDI, TARGET_LONG_BITS == 64, TCG_REG_X3, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); + /* Add any "high bits" from the tlb offset to the env address into X2, to take advantage of the LSL12 form of the ADDI instruction. X2 = env + (tlb_offset & 0xfff000) */ - tcg_fmt_Rdn_aimm(s, INSN_ADDI, 1, TCG_REG_X2, base, tlb_offset & 0xfff000); + if (tlb_offset & 0xfff000) { + tcg_fmt_Rdn_aimm(s, INSN_ADDI, 1, TCG_REG_X2, base, + tlb_offset & 0xfff000); + base = TCG_REG_X2; + } + /* Merge the tlb index contribution into X2. - X2 = X2 + (X0 << CPU_TLB_ENTRY_BITS) */ - tcg_fmt_Rdnm_lsl(s, INSN_ADD, 1, TCG_REG_X2, TCG_REG_X2, + X2 = base + (X0 << CPU_TLB_ENTRY_BITS) */ + tcg_fmt_Rdnm_lsl(s, INSN_ADD, 1, TCG_REG_X2, base, TCG_REG_X0, CPU_TLB_ENTRY_BITS); + /* Merge "low bits" from tlb offset, load the tlb comparator into X0. X0 = load [X2 + (tlb_offset & 0x000fff)] */ tcg_out_ldst(s, TARGET_LONG_BITS == 64 ? LDST_64 : LDST_32, LDST_LD, TCG_REG_X0, TCG_REG_X2, (tlb_offset & 0xfff)); + /* Load the tlb addend. Do that early to avoid stalling. X1 = load [X2 + (tlb_offset & 0xfff) + offsetof(addend)] */ tcg_out_ldst(s, LDST_64, LDST_LD, TCG_REG_X1, TCG_REG_X2, (tlb_offset & 0xfff) + (offsetof(CPUTLBEntry, addend)) - (is_read ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write))); + /* Perform the address comparison. */ tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3, 0); - *label_ptr = s->code_ptr; + /* If not equal, we jump to the slow path. */ + *label_ptr = s->code_ptr; tcg_out_goto_cond_noaddr(s, TCG_COND_NE); }