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X-Received-From: 2607:f8b0:400e:c01::22f Cc: peter.maydell@linaro.org, claudio.fontana@gmail.com Subject: [Qemu-devel] [PATCH v4 20/33] tcg-aarch64: Support div, rem X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org For remainder, generic code will produce mul+sub, whereas we can implement with msub. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 51 +++++++++++++++++++++++++++++++++++++++--------- tcg/aarch64/tcg-target.h | 8 ++++---- 2 files changed, 46 insertions(+), 13 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index b7f7fa5..c44f404 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -302,6 +302,12 @@ typedef enum { INSN_RORV = 0x1ac02c00, INSN_SMULH = 0x9b407c00, INSN_UMULH = 0x9bc07c00, + INSN_UDIV = 0x1ac00800, + INSN_SDIV = 0x1ac00c00, + + /* Data-processing (3 source) instructions */ + INSN_MADD = 0x1b000000, + INSN_MSUB = 0x1b008000, /* Bitfield instructions */ INSN_BFM = 0x33000000, @@ -416,6 +422,13 @@ static inline void tcg_fmt_Rdnm(TCGContext *s, AArch64Insn insn, TCGType sf, tcg_out32(s, insn | sf << 31 | rm << 16 | rn << 5 | rd); } +/* This function is used for the Multiply instruction group. */ +static inline void tcg_fmt_Rdnma(TCGContext *s, AArch64Insn insn, TCGType sf, + TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra) +{ + tcg_out32(s, insn | sf << 31 | rm << 16 | ra << 10 | rn << 5 | rd); +} + /* This function is used for the Arithmetic (immediate) instruction group. The value of AIMM must be appropriate for encoding in the shift+imm12 fields. */ @@ -621,14 +634,6 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, arg, arg1, arg2); } -static inline void tcg_out_mul(TCGContext *s, TCGType ext, - TCGReg rd, TCGReg rn, TCGReg rm) -{ - /* Using MADD 0x1b000000 with Ra = wzr alias MUL 0x1b007c00 */ - unsigned int base = ext ? 0x9b007c00 : 0x1b007c00; - tcg_out32(s, base | rm << 16 | rn << 5 | rd); -} - static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn, unsigned int a, unsigned int b) { @@ -1425,7 +1430,27 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mul_i64: case INDEX_op_mul_i32: - tcg_out_mul(s, ext, a0, a1, a2); + tcg_fmt_Rdnma(s, INSN_MADD, ext, a0, a1, a2, TCG_REG_XZR); + break; + + case INDEX_op_div_i64: + case INDEX_op_div_i32: + tcg_fmt_Rdnm(s, INSN_SDIV, ext, a0, a1, a2); + break; + case INDEX_op_divu_i64: + case INDEX_op_divu_i32: + tcg_fmt_Rdnm(s, INSN_UDIV, ext, a0, a1, a2); + break; + + case INDEX_op_rem_i64: + case INDEX_op_rem_i32: + tcg_fmt_Rdnm(s, INSN_SDIV, ext, TCG_REG_TMP, a1, a2); + tcg_fmt_Rdnma(s, INSN_MSUB, ext, a0, TCG_REG_TMP, a2, a1); + break; + case INDEX_op_remu_i64: + case INDEX_op_remu_i32: + tcg_fmt_Rdnm(s, INSN_UDIV, ext, TCG_REG_TMP, a1, a2); + tcg_fmt_Rdnma(s, INSN_MSUB, ext, a0, TCG_REG_TMP, a2, a1); break; case INDEX_op_shl_i64: @@ -1658,6 +1683,14 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_sub_i64, { "r", "rZ", "rA" } }, { INDEX_op_mul_i32, { "r", "r", "r" } }, { INDEX_op_mul_i64, { "r", "r", "r" } }, + { INDEX_op_div_i32, { "r", "r", "r" } }, + { INDEX_op_div_i64, { "r", "r", "r" } }, + { INDEX_op_divu_i32, { "r", "r", "r" } }, + { INDEX_op_divu_i64, { "r", "r", "r" } }, + { INDEX_op_rem_i32, { "r", "r", "r" } }, + { INDEX_op_rem_i64, { "r", "r", "r" } }, + { INDEX_op_remu_i32, { "r", "r", "r" } }, + { INDEX_op_remu_i64, { "r", "r", "r" } }, { INDEX_op_and_i32, { "r", "r", "rwL" } }, { INDEX_op_and_i64, { "r", "r", "rL" } }, { INDEX_op_or_i32, { "r", "r", "rwL" } }, diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 52c6c23..8b55ff9 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -39,8 +39,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 /* optional instructions */ -#define TCG_TARGET_HAS_div_i32 0 -#define TCG_TARGET_HAS_rem_i32 0 +#define TCG_TARGET_HAS_div_i32 1 +#define TCG_TARGET_HAS_rem_i32 1 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 @@ -64,8 +64,8 @@ typedef enum { #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_div_i64 0 -#define TCG_TARGET_HAS_rem_i64 0 +#define TCG_TARGET_HAS_div_i64 1 +#define TCG_TARGET_HAS_rem_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 #define TCG_TARGET_HAS_ext16s_i64 1 #define TCG_TARGET_HAS_ext32s_i64 1