From patchwork Sat Sep 14 15:51:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Herv=C3=A9_Poussineau?= X-Patchwork-Id: 274927 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 119B42C0129 for ; Sun, 15 Sep 2013 01:53:14 +1000 (EST) Received: from localhost ([::1]:53790 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKs9o-0004p5-0D for incoming@patchwork.ozlabs.org; Sat, 14 Sep 2013 11:53:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48608) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKs71-0000d4-VZ for qemu-devel@nongnu.org; Sat, 14 Sep 2013 11:50:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VKs6q-0004w9-7x for qemu-devel@nongnu.org; Sat, 14 Sep 2013 11:50:19 -0400 Received: from smtp2-g21.free.fr ([2a01:e0c:1:1599::11]:37759) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKs6p-0004v4-KL for qemu-devel@nongnu.org; Sat, 14 Sep 2013 11:50:08 -0400 Received: from localhost.localdomain (unknown [82.227.227.196]) by smtp2-g21.free.fr (Postfix) with ESMTP id 0A4904B01E9; Sat, 14 Sep 2013 17:50:01 +0200 (CEST) From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= To: qemu-devel@nongnu.org Date: Sat, 14 Sep 2013 17:51:07 +0200 Message-Id: <1379173870-10974-4-git-send-email-hpoussin@reactos.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1379173870-10974-1-git-send-email-hpoussin@reactos.org> References: <1379173870-10974-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a01:e0c:1:1599::11 Cc: Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= Subject: [Qemu-devel] [PATCH v2 3/5] lsi: ignore write accesses to CTEST0 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org 53C895A datasheet says that this register is read/write, and that the value returned on read access is dependant of DMA FIFO state. However, nothing is said for written value. 53C810A datasheet gives more insight about this register: "This was a general purpose read/write register in previous SYM53C8XX family chips. Although it is still a read/write register, Symbios reserves the right to use these bits for future 53C8XX family enhancements." This prevents going to the default case, which prints an error message. Signed-off-by: Hervé Poussineau --- hw/scsi/lsi53c895a.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c index 764feaa..a9a9eca 100644 --- a/hw/scsi/lsi53c895a.c +++ b/hw/scsi/lsi53c895a.c @@ -1749,6 +1749,9 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) case 0x17: /* MBOX1 */ s->mbox1 = val; break; + case 0x18: /* CTEST0 */ + /* nothing to do */ + break; case 0x1a: /* CTEST2 */ s->ctest2 = val & LSI_CTEST2_PCICIE; break;