[3/4] lsi: ignore write accesses to CTEST0 registers

Message ID 1379101857-27500-4-git-send-email-hpoussin@reactos.org
State New
Headers show

Commit Message

Hervé Poussineau Sept. 13, 2013, 7:50 p.m.
53C895A datasheet says that this register is read/write, and that the value
returned on read access is dependant of DMA FIFO state. However, nothing is
said for written value.

53C810A datasheet gives more insight about this register:
"This was a general purpose read/write register in previous SYM53C8XX
family chips. Although it is still a read/write register, Symbios reserves
the right to use these bits for future 53C8XX family enhancements."

This prevents going to the default case, which prints an error message.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
 hw/scsi/lsi53c895a.c |    3 +++
 1 file changed, 3 insertions(+)


diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
index 764feaa..a9a9eca 100644
--- a/hw/scsi/lsi53c895a.c
+++ b/hw/scsi/lsi53c895a.c
@@ -1749,6 +1749,9 @@  static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
     case 0x17: /* MBOX1 */
         s->mbox1 = val;
+    case 0x18: /* CTEST0 */
+        /* nothing to do */
+        break;
     case 0x1a: /* CTEST2 */
 	s->ctest2 = val & LSI_CTEST2_PCICIE;