From patchwork Fri Sep 13 09:40:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Cross X-Patchwork-Id: 274698 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 271E32C0189 for ; Fri, 13 Sep 2013 19:57:33 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756645Ab3IMJ5X (ORCPT ); Fri, 13 Sep 2013 05:57:23 -0400 Received: from mail1.g1.pair.com ([66.39.3.162]:44194 "EHLO mail1.g1.pair.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755774Ab3IMJ5W (ORCPT ); Fri, 13 Sep 2013 05:57:22 -0400 Received: from xobs-novena.novalocal (unknown [210.23.25.254]) by mail1.g1.pair.com (Postfix) with ESMTPSA id C232C29461; Fri, 13 Sep 2013 05:57:18 -0400 (EDT) From: Sean Cross To: devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Sascha Hauer , Zhu Richard-R65037 , Shawn Guo , Sean Cross Subject: [PATCH v4 2/3] ARM: imx6q: Add PCIe bits to GPR syscon definition Date: Fri, 13 Sep 2013 09:40:21 +0000 Message-Id: <1379065222-7275-3-git-send-email-xobs@kosagi.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1379065222-7275-1-git-send-email-xobs@kosagi.com> References: <1379065222-7275-1-git-send-email-xobs@kosagi.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org PCIe requires additional bits be defined for GPR8 and GPR12. Signed-off-by: Sean Cross --- include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index b6bdcd6..1bf1fe9 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -241,6 +241,12 @@ #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3F << 0) +#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3F << 6) +#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3F << 12) +#define IMX6Q_GPR8_TX_SWING_FULL (0x7F << 18) +#define IMX6Q_GPR8_TX_SWING_LOW (0x7F << 25) + #define IMX6Q_GPR9_TZASC2_BYP BIT(1) #define IMX6Q_GPR9_TZASC1_BYP BIT(0) @@ -273,7 +279,9 @@ #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) +#define IMX6Q_GPR12_DEVICE_TYPE (0xF << 12) #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) +#define IMX6Q_GPR12_LOS_LEVEL (0x1F << 4) #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)