Patchwork [U-Boot,1/2] powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socs

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Submitter ramneek mehresh
Date Sept. 12, 2013, 11:05 a.m.
Message ID <1378983949-25525-2-git-send-email-ramneek.mehresh@freescale.com>
Download mbox | patch
Permalink /patch/274509/
State Superseded
Delegated to: York Sun
Headers show

Comments

ramneek mehresh - Sept. 12, 2013, 11:05 a.m.
CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for
initializing all USB controllers on a given platform. This
macro is defined for all 85xx socs

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/fdt.c            |  6 ++++--
 arch/powerpc/include/asm/config_mpc85xx.h | 24 ++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 2 deletions(-)
York Sun - Sept. 27, 2013, 6:54 p.m.
On 09/12/2013 04:05 AM, Ramneek Mehresh wrote:
> CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for
> initializing all USB controllers on a given platform. This
> macro is defined for all 85xx socs
> 
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> ---

Can you rebase your patch to u-boot-mpc85xx/next branch? I have some
conflicts and am not sure if I get it right, especialy for T4240 part in
config_mpc85xx.h.

York

Patch

diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index eb7cbbc..9273745 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -15,7 +15,9 @@ 
 #include <phy.h>
 #include <hwconfig.h>
 
-#define FSL_MAX_NUM_USB_CTRLS	2
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#endif
 
 #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
 static int ft_del_cpuhandle(void *blob, int cpuhandle)
@@ -128,7 +130,7 @@  void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 	char str[5];
 	int i, j;
 
-	for (i = 1; i <= FSL_MAX_NUM_USB_CTRLS; i++) {
+	for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
 		int mode_idx = -1, phy_idx = -1;
 		snprintf(str, 5, "%s%d", "usb", i);
 		if (hwconfig(str)) {
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 15e44de..b395e1c 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -127,6 +127,7 @@ 
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
@@ -146,6 +147,7 @@ 
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -154,6 +156,7 @@ 
 #elif defined(CONFIG_P1012)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -169,6 +172,7 @@ 
 #elif defined(CONFIG_P1013)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
@@ -186,6 +190,7 @@ 
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
@@ -200,6 +205,7 @@ 
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_QMAN_NUM_PORTALS	3
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
@@ -216,6 +222,7 @@ 
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
 #elif defined(CONFIG_P1021)
 #define CONFIG_MAX_CPUS			2
@@ -230,6 +237,7 @@ 
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
 #elif defined(CONFIG_P1022)
 #define CONFIG_MAX_CPUS			2
@@ -237,6 +245,7 @@ 
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -249,6 +258,7 @@ 
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_QMAN_NUM_PORTALS	3
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
@@ -265,6 +275,7 @@ 
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -273,6 +284,7 @@ 
 #elif defined(CONFIG_P1025)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -290,6 +302,7 @@ 
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
@@ -307,6 +320,7 @@ 
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -319,6 +333,7 @@ 
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
@@ -361,6 +376,7 @@ 
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
@@ -394,6 +410,7 @@ 
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_SYS_NUM_FM2_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
@@ -441,6 +458,7 @@ 
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
@@ -476,6 +494,7 @@ 
 #define CONFIG_SYS_NUM_FM2_DTSEC	5
 #define CONFIG_SYS_NUM_FM2_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
@@ -500,6 +519,7 @@ 
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
@@ -515,6 +535,7 @@ 
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_DSP_DDR_ADDR	0x40000000
 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR	0xc0000000
@@ -542,6 +563,7 @@ 
 #define CONFIG_SYS_NUM_FM2_DTSEC	8
 #define CONFIG_SYS_NUM_FM2_10GEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #else
 #define CONFIG_MAX_CPUS			8
 #define CONFIG_SYS_NUM_FM1_DTSEC	7
@@ -588,6 +610,7 @@ 
 #define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_FMAN_V3
@@ -632,6 +655,7 @@ 
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4