From patchwork Wed Sep 11 11:17:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Longchamp X-Patchwork-Id: 274250 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5A2B62C0167 for ; Wed, 11 Sep 2013 21:19:54 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4CEC54A088; Wed, 11 Sep 2013 13:19:41 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id c78kKQfACh7X; Wed, 11 Sep 2013 13:19:41 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C53E74A0D0; Wed, 11 Sep 2013 13:18:31 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 211984A0A5 for ; Wed, 11 Sep 2013 13:18:13 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rW3XxNR9872X for ; Wed, 11 Sep 2013 13:18:11 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-de.keymile.com (mail-de.keymile.com [195.8.104.250]) by theia.denx.de (Postfix) with ESMTPS id 387024A087 for ; Wed, 11 Sep 2013 13:17:59 +0200 (CEST) Received: from [10.9.1.54] (port=41358 helo=mailrelay.de.keymile.net) by mail-de.keymile.com with esmtp (Exim 4.76) (envelope-from ) id 1VJiQm-0008Bu-2V; Wed, 11 Sep 2013 13:17:56 +0200 Received: from chber1-10533x.keymile.net (chber1-10533x.keymile.net [172.31.40.3]) by mailrelay.de.keymile.net (8.12.2/8.12.2) with ESMTP id r8BBFT1g006908; Wed, 11 Sep 2013 13:15:37 +0200 (MEST) From: Valentin Longchamp To: Andy Fleming , Scott Wood , York Sun Date: Wed, 11 Sep 2013 13:17:44 +0200 Message-Id: <1378898265-10818-11-git-send-email-valentin.longchamp@keymile.com> X-Mailer: git-send-email 1.8.0.1 In-Reply-To: <1378898265-10818-1-git-send-email-valentin.longchamp@keymile.com> References: <1378898265-10818-1-git-send-email-valentin.longchamp@keymile.com> Cc: U-Boot Mailing List , Holger Brunck , Valentin Longchamp Subject: [U-Boot] [PATCH v3 10/11] fsl/mpc85xx: define common serdes_clock_to_string function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This allows to share some common code for the boards that use a corenet base SoC. Two different versions of the function are available in fsl_corenet_serdes.c and fsl_corenet2_serdes.c files. Signed-off-by: Valentin Longchamp --- Changes in v3: None Changes in v2: None arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 21 +++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 17 +++++++++++++++++ arch/powerpc/include/asm/fsl_serdes.h | 1 + board/freescale/b4860qds/b4860qds.c | 16 ---------------- board/freescale/corenet_ds/corenet_ds.c | 14 -------------- board/freescale/p2041rdb/p2041rdb.c | 14 -------------- board/freescale/t4qds/t4240qds.c | 16 ---------------- 7 files changed, 39 insertions(+), 60 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 39d9409..25db899 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -201,3 +201,24 @@ void fsl_serdes_init(void) #endif } + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.1328123"; + default: +#if defined(CONFIG_T4240QDS) + return "???"; +#else + return "122.88"; +#endif + } +} + diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 680b522..ba22f90 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -858,3 +858,20 @@ void fsl_serdes_init(void) } #endif } + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.1328123"; + default: + return "150"; + } +} + diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 1106d28..cce892c 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -86,6 +86,7 @@ enum srds { int is_serdes_configured(enum srds_prtcl device); void fsl_serdes_init(void); +const char *serdes_clock_to_string(u32 clock); #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index f74651c..f6b012d 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -457,22 +457,6 @@ static int serdes_refclock(u8 sw, u8 sdclk) return ret; } -static const char *serdes_clock_to_string(u32 clock) -{ - switch (clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - case SRDS_PLLCR0_RFCK_SEL_161_13: - return "161.13"; - default: - return "122.88"; - } -} - #define NUM_SRDS_BANKS 2 int misc_init_r(void) diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 60e2100..9212372 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -127,20 +127,6 @@ int board_early_init_r(void) return 0; } -static const char *serdes_clock_to_string(u32 clock) -{ - switch(clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - default: - return "150"; - } -} - #define NUM_SRDS_BANKS 3 int misc_init_r(void) diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 60694a6..8554512 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -155,20 +155,6 @@ unsigned long get_board_sys_clk(unsigned long dummy) } } -static const char *serdes_clock_to_string(u32 clock) -{ - switch (clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - default: - return "150"; - } -} - #define NUM_SRDS_BANKS 2 int misc_init_r(void) diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index 0c1a4fb..79b770b 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -608,22 +608,6 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -static const char *serdes_clock_to_string(u32 clock) -{ - switch (clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - case SRDS_PLLCR0_RFCK_SEL_161_13: - return "161.1328125"; - default: - return "???"; - } -} - int misc_init_r(void) { u8 sw;