Patchwork [U-Boot,06/12,V3] Exynos5420: Alter UNCON and UFCON for 5420

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Submitter Rajeshwari Birje
Date Sept. 11, 2013, 10:01 a.m.
Message ID <1378893684-27733-7-git-send-email-rajeshwari.s@samsung.com>
Download mbox | patch
Permalink /patch/274222/
State Changes Requested
Delegated to: Minkyu Kang
Headers show

Comments

Rajeshwari Birje - Sept. 11, 2013, 10:01 a.m.
From: Akshay Saraswat <akshay.s@samsung.com>

This patch modifies UNCON and UFCON values to make s5p
serial support exynos5420 by doing following changes:
*  Enable Rx time-out interrupts.
*  Make Rx time-out interrupt interval = 32 frame time.
*  Enable DMA mode.
*  Enable FIFO.
*  Make Rx FIFO Trigger level 64, 16 and 4 bytes for channels
   channels 0, 1 and 2/3 respectively.
*  Make Tx FIFO Trigger level 32, 8 and 2 bytes for channels
   channels 0, 1 and 2/3 respectively.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
---
Changes in V2:
	- None
Changes in V3:
	- None
 drivers/serial/serial_s5p.c | 6 ++++++
 1 file changed, 6 insertions(+)
Simon Glass - Sept. 19, 2013, 6:01 a.m.
Hi Rajeshwari,

On Wed, Sep 11, 2013 at 4:01 AM, Rajeshwari S Shinde <
rajeshwari.s@samsung.com> wrote:

> From: Akshay Saraswat <akshay.s@samsung.com>
>
> This patch modifies UNCON and UFCON values to make s5p
> serial support exynos5420 by doing following changes:
> *  Enable Rx time-out interrupts.
> *  Make Rx time-out interrupt interval = 32 frame time.
> *  Enable DMA mode.
> *  Enable FIFO.
> *  Make Rx FIFO Trigger level 64, 16 and 4 bytes for channels
>    channels 0, 1 and 2/3 respectively.
> *  Make Tx FIFO Trigger level 32, 8 and 2 bytes for channels
>    channels 0, 1 and 2/3 respectively.
>
> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>
---
> Changes in V2:
>         - None
> Changes in V3:
>         - None
>  drivers/serial/serial_s5p.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
> index f98b422..b939084 100644
> --- a/drivers/serial/serial_s5p.c
> +++ b/drivers/serial/serial_s5p.c
> @@ -107,6 +107,12 @@ int serial_init_dev(const int dev_index)
>         writel(0x3, &uart->ulcon);
>         /* No interrupts, no DMA, pure polling */
>         writel(0x245, &uart->ucon);
> +       if (proid_is_exynos5420()) {
> +               /* Enable interrupts and Enable DMA mode */
> +               writel(0x3045, &uart->ucon);
> +               /* enable FIFOs */
> +               writel(0x111, &uart->ufcon);
> +       }
>

Really I think this should be a device tree difference, but I suppose it is
something we can address later. Do any Exynos5 boards NOT use device tree?

Don't you also need to adjust serial_getc/putc_dev() to check the FIFO
rather than just the holding register? See Chromium tree for what was done
there. (I may be wrong, just checking).


>         serial_setbrg_dev(dev_index);
>
> --
> 1.7.12.4
>
>
Regards,
Simon

Patch

diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index f98b422..b939084 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -107,6 +107,12 @@  int serial_init_dev(const int dev_index)
 	writel(0x3, &uart->ulcon);
 	/* No interrupts, no DMA, pure polling */
 	writel(0x245, &uart->ucon);
+	if (proid_is_exynos5420()) {
+		/* Enable interrupts and Enable DMA mode */
+		writel(0x3045, &uart->ucon);
+		/* enable FIFOs */
+		writel(0x111, &uart->ufcon);
+	}
 
 	serial_setbrg_dev(dev_index);