Message ID | 1378875514-951-1-git-send-email-shh.xie@gmail.com |
---|---|
State | Accepted |
Delegated to: | York Sun |
Headers | show |
On 09/10/2013 09:58 PM, shh.xie@gmail.com wrote: > From: Shaohui Xie <Shaohui.Xie@freescale.com> > > Default configuration has been changed, the most important one is DDR > ref_clock which is changed from 66.67MHz to 133.33MHz. so the ratio need to > change from 24x to 12x to keep the DDR frequency. There are also some > other optimise to align with default configuration. > > Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> > --- Applied to u-boot-mpc85xx/next, pending merging to u-boot-mpc85xx/master branch. York
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg index 6ac95ff..74df01a 100644 --- a/board/freescale/t4qds/t4_rcw.cfg +++ b/board/freescale/t4qds/t4_rcw.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 010e0100 #serdes protocol 1_28_6_12 -14180019 0c101916 00000000 00000000 -04383060 30548c00 6c020000 19000000 -00000000 ee0000ee 00000000 000187fc -00000000 00000000 00000000 00000018 +120c0019 0c101915 00000000 00000000 +04383063 30548c00 6c020000 1d000000 +00000000 ee0000ee 00000000 000307fc +00000000 00000000 00000000 00000020