Patchwork [v4] powerpc/mpc85xx: Update the clock device tree nodes

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Submitter tang yuantian
Date Sept. 11, 2013, 6:57 a.m.
Message ID <1378882632-9053-1-git-send-email-Yuantian.Tang@freescale.com>
Download mbox | patch
Permalink /patch/274134/
State Superseded
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tang yuantian - Sept. 11, 2013, 6:57 a.m.
From: Tang Yuantian <yuantian.tang@freescale.com>

The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
v4:
	- add binding document
	- update compatible string
	- update the reg property
v3:
	- fix typo
v2:
	- add t4240, b4420, b4860 support
	- remove pll/4 clock from p2041, p3041 and p5020 board

 .../devicetree/bindings/clock/corenet-clock.txt    |  80 +++++++++++++++
 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi        |  34 ++++++-
 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi         |   2 +
 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi        |  34 ++++++-
 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi         |   4 +
 arch/powerpc/boot/dts/fsl/p2041si-post.dtsi        |  59 ++++++++++-
 arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi         |   4 +
 arch/powerpc/boot/dts/fsl/p3041si-post.dtsi        |  59 ++++++++++-
 arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi         |   4 +
 arch/powerpc/boot/dts/fsl/p4080si-post.dtsi        | 111 ++++++++++++++++++++-
 arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi         |   8 ++
 arch/powerpc/boot/dts/fsl/p5020si-post.dtsi        |  41 +++++++-
 arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi         |   2 +
 arch/powerpc/boot/dts/fsl/p5040si-post.dtsi        |  59 ++++++++++-
 arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi         |   4 +
 arch/powerpc/boot/dts/fsl/t4240si-post.dtsi        |  84 +++++++++++++++-
 arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi         |  12 +++
 17 files changed, 593 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/corenet-clock.txt
Scott Wood - Sept. 12, 2013, 1:10 a.m.
On Wed, 2013-09-11 at 14:57 +0800, Yuantian.Tang@freescale.com wrote:
> From: Tang Yuantian <yuantian.tang@freescale.com>
> 
> The following SoCs will be affected: p2041, p3041, p4080,
> p5020, p5040, b4420, b4860, t4240
> 
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> v4:
> 	- add binding document
> 	- update compatible string
> 	- update the reg property
> v3:
> 	- fix typo
> v2:
> 	- add t4240, b4420, b4860 support
> 	- remove pll/4 clock from p2041, p3041 and p5020 board
> 
>  .../devicetree/bindings/clock/corenet-clock.txt    |  80 +++++++++++++++
>  arch/powerpc/boot/dts/fsl/b4420si-post.dtsi        |  34 ++++++-
>  arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi         |   2 +
>  arch/powerpc/boot/dts/fsl/b4860si-post.dtsi        |  34 ++++++-
>  arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi         |   4 +
>  arch/powerpc/boot/dts/fsl/p2041si-post.dtsi        |  59 ++++++++++-
>  arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi         |   4 +
>  arch/powerpc/boot/dts/fsl/p3041si-post.dtsi        |  59 ++++++++++-
>  arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi         |   4 +
>  arch/powerpc/boot/dts/fsl/p4080si-post.dtsi        | 111 ++++++++++++++++++++-
>  arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi         |   8 ++
>  arch/powerpc/boot/dts/fsl/p5020si-post.dtsi        |  41 +++++++-
>  arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi         |   2 +
>  arch/powerpc/boot/dts/fsl/p5040si-post.dtsi        |  59 ++++++++++-
>  arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi         |   4 +
>  arch/powerpc/boot/dts/fsl/t4240si-post.dtsi        |  84 +++++++++++++++-
>  arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi         |  12 +++
>  17 files changed, 593 insertions(+), 8 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/corenet-clock.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt b/Documentation/devicetree/bindings/clock/corenet-clock.txt
> new file mode 100644
> index 0000000..51eab75
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt
> @@ -0,0 +1,80 @@
> +Device Tree Clock bindings for Freescale PowerPC corenet platform
> +
> +This binding uses the common clock binding[1].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible : shall be one or more of the following:

Shall include...

> +	- "fsl,<chip>-clockgen": for chip specific clock block
> +	- "fsl,qoriq-clockgen-[1,2].0": for chassis 1.0 and 2.0 clock
> +		block respectively.
> +	- "fsl,qoriq-chassis[1,2]-core-pll" - for a core PLL clock
> +	- "fsl,qoriq-chassis[1,2]-core-mux" - for a core multiplexer clock.
> +		Divided from the core PLL clock

Hmm, there's a bit of a mismatch here between "chassis2" and the "2.0"
on the clockgen node... perhaps it should be "fsl,qoriq-core-pll-2.0",
etc.

> +	- "fixed-clock" - from common clock binding; should be output clock
> +		of oscillator
> +- reg : shall be the control register offset from clock block base address.

This description of "reg" is overly specific (assumes how the parent
node's ranges are set up), incomplete (there's a size as well as the
offset), and does not apply to the clockgen node itself (you probably
shouldn't lump them together like this).

> +- clocks : shall be the input parent clock phandle for the clock.

Not required on the clockgen node

-Scott
tang yuantian - Sept. 12, 2013, 1:31 a.m.
> -----Original Message-----

> From: Wood Scott-B07421

> Sent: 2013年9月12日 星期四 9:10

> To: Tang Yuantian-B29983

> Cc: galak@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;

> devicetree@vger.kernel.org; Li Yang-Leo-R58472

> Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device tree

> nodes

> 

> On Wed, 2013-09-11 at 14:57 +0800, Yuantian.Tang@freescale.com wrote:

> > From: Tang Yuantian <yuantian.tang@freescale.com>

> >

> > The following SoCs will be affected: p2041, p3041, p4080, p5020,

> > p5040, b4420, b4860, t4240

> >

> > Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>

> > Signed-off-by: Li Yang <leoli@freescale.com>

> > ---

> > v4:

> > 	- add binding document

> > 	- update compatible string

> > 	- update the reg property

> > v3:

> > 	- fix typo

> > v2:

> > 	- add t4240, b4420, b4860 support

> > 	- remove pll/4 clock from p2041, p3041 and p5020 board

> >

> >  .../devicetree/bindings/clock/corenet-clock.txt    |  80

> +++++++++++++++

> >  arch/powerpc/boot/dts/fsl/b4420si-post.dtsi        |  34 ++++++-

> >  arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi         |   2 +

> >  arch/powerpc/boot/dts/fsl/b4860si-post.dtsi        |  34 ++++++-

> >  arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi         |   4 +

> >  arch/powerpc/boot/dts/fsl/p2041si-post.dtsi        |  59 ++++++++++-

> >  arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi         |   4 +

> >  arch/powerpc/boot/dts/fsl/p3041si-post.dtsi        |  59 ++++++++++-

> >  arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi         |   4 +

> >  arch/powerpc/boot/dts/fsl/p4080si-post.dtsi        | 111

> ++++++++++++++++++++-

> >  arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi         |   8 ++

> >  arch/powerpc/boot/dts/fsl/p5020si-post.dtsi        |  41 +++++++-

> >  arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi         |   2 +

> >  arch/powerpc/boot/dts/fsl/p5040si-post.dtsi        |  59 ++++++++++-

> >  arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi         |   4 +

> >  arch/powerpc/boot/dts/fsl/t4240si-post.dtsi        |  84

> +++++++++++++++-

> >  arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi         |  12 +++

> >  17 files changed, 593 insertions(+), 8 deletions(-)  create mode

> > 100644 Documentation/devicetree/bindings/clock/corenet-clock.txt

> >

> > diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt

> > b/Documentation/devicetree/bindings/clock/corenet-clock.txt

> > new file mode 100644

> > index 0000000..51eab75

> > --- /dev/null

> > +++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt

> > @@ -0,0 +1,80 @@

> > +Device Tree Clock bindings for Freescale PowerPC corenet platform

> > +

> > +This binding uses the common clock binding[1].

> > +

> > +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

> > +

> > +Required properties:

> > +- compatible : shall be one or more of the following:

> 

> Shall include...

> 

> > +	- "fsl,<chip>-clockgen": for chip specific clock block

> > +	- "fsl,qoriq-clockgen-[1,2].0": for chassis 1.0 and 2.0 clock

> > +		block respectively.

> > +	- "fsl,qoriq-chassis[1,2]-core-pll" - for a core PLL clock

> > +	- "fsl,qoriq-chassis[1,2]-core-mux" - for a core multiplexer clock.

> > +		Divided from the core PLL clock

> 

> Hmm, there's a bit of a mismatch here between "chassis2" and the "2.0"

> on the clockgen node... perhaps it should be "fsl,qoriq-core-pll-2.0",

> etc.

> 

> > +	- "fixed-clock" - from common clock binding; should be output clock

> > +		of oscillator

> > +- reg : shall be the control register offset from clock block base

> address.

> 

> This description of "reg" is overly specific (assumes how the parent

> node's ranges are set up), incomplete (there's a size as well as the

> offset), and does not apply to the clockgen node itself (you probably

> shouldn't lump them together like this).

> 

Do you mean I should explain the REG of clockgen and its child node respectively?

> > +- clocks : shall be the input parent clock phandle for the clock.

> 

> Not required on the clockgen node

> 

Required by child node of clockgen.

Regards,
Yuantian
> -Scott

>
Scott Wood - Sept. 12, 2013, 2:44 p.m.
On Wed, 2013-09-11 at 20:31 -0500, Tang Yuantian-B29983 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: 2013年9月12日 星期四 9:10
> > To: Tang Yuantian-B29983
> > Cc: galak@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
> > devicetree@vger.kernel.org; Li Yang-Leo-R58472
> > Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device tree
> > nodes
> > 
> > This description of "reg" is overly specific (assumes how the parent
> > node's ranges are set up), incomplete (there's a size as well as the
> > offset), and does not apply to the clockgen node itself (you probably
> > shouldn't lump them together like this).
> > 
> Do you mean I should explain the REG of clockgen and its child node respectively?
> 
> > > +- clocks : shall be the input parent clock phandle for the clock.
> > 
> > Not required on the clockgen node
> > 
> Required by child node of clockgen.

My point is that you're lumping several different types of nodes
together with one binding, when some parts of the binding are not
applicable to the clockgen node.

-Scott
tang yuantian - Sept. 13, 2013, 2:50 a.m.
> -----Original Message-----

> From: Wood Scott-B07421

> Sent: 2013年9月12日 星期四 22:44

> To: Tang Yuantian-B29983

> Cc: Wood Scott-B07421; galak@kernel.crashing.org; linuxppc-

> dev@lists.ozlabs.org; devicetree@vger.kernel.org; Li Yang-Leo-R58472

> Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device tree

> nodes

> 

> On Wed, 2013-09-11 at 20:31 -0500, Tang Yuantian-B29983 wrote:

> > > -----Original Message-----

> > > From: Wood Scott-B07421

> > > Sent: 2013年9月12日 星期四 9:10

> > > To: Tang Yuantian-B29983

> > > Cc: galak@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;

> > > devicetree@vger.kernel.org; Li Yang-Leo-R58472

> > > Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device

> > > tree nodes

> > >

> > > This description of "reg" is overly specific (assumes how the parent

> > > node's ranges are set up), incomplete (there's a size as well as the

> > > offset), and does not apply to the clockgen node itself (you

> > > probably shouldn't lump them together like this).

> > >

> > Do you mean I should explain the REG of clockgen and its child node

> respectively?

> >

> > > > +- clocks : shall be the input parent clock phandle for the clock.

> > >

> > > Not required on the clockgen node

> > >

> > Required by child node of clockgen.

> 

> My point is that you're lumping several different types of nodes together

> with one binding, when some parts of the binding are not applicable to

> the clockgen node.

> 

Not several, just two types of nodes.
One is clockgen node, the other is PLL and mux nodes.

The reason they lumped together is that the clockgen node is not only IP block
Node but also a clock provider node.

At first, I want to add a extra fixed-clock node and move the clock-frequency of clockgen 
Node to it, but it is against the backward compatibility which I think it is not a big deal,
Because nobody hasn't used it yet.
If I add a extra node with the clock-frequency property and don't move the
clock-frequency property of clockgen, that would be redundant because both clockgen node
and the extra node have the same clock-frequency node.
So, I choose what I did now.
 
Could you give me some suggestions on this?
Regards,
Yuantian

> -Scott

>
Scott Wood - Sept. 16, 2013, 8:39 p.m.
On Thu, 2013-09-12 at 21:50 -0500, Tang Yuantian-B29983 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: 2013年9月12日 星期四 22:44
> > To: Tang Yuantian-B29983
> > Cc: Wood Scott-B07421; galak@kernel.crashing.org; linuxppc-
> > dev@lists.ozlabs.org; devicetree@vger.kernel.org; Li Yang-Leo-R58472
> > Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device tree
> > nodes
> > 
> > On Wed, 2013-09-11 at 20:31 -0500, Tang Yuantian-B29983 wrote:
> > > > -----Original Message-----
> > > > From: Wood Scott-B07421
> > > > Sent: 2013年9月12日 星期四 9:10
> > > > To: Tang Yuantian-B29983
> > > > Cc: galak@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
> > > > devicetree@vger.kernel.org; Li Yang-Leo-R58472
> > > > Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device
> > > > tree nodes
> > > >
> > > > This description of "reg" is overly specific (assumes how the parent
> > > > node's ranges are set up), incomplete (there's a size as well as the
> > > > offset), and does not apply to the clockgen node itself (you
> > > > probably shouldn't lump them together like this).
> > > >
> > > Do you mean I should explain the REG of clockgen and its child node
> > respectively?
> > >
> > > > > +- clocks : shall be the input parent clock phandle for the clock.
> > > >
> > > > Not required on the clockgen node
> > > >
> > > Required by child node of clockgen.
> > 
> > My point is that you're lumping several different types of nodes together
> > with one binding, when some parts of the binding are not applicable to
> > the clockgen node.
> > 
> Not several, just two types of nodes.
> One is clockgen node, the other is PLL and mux nodes.

clockgen + PLL + mux = 3 = several :-)

> The reason they lumped together is that the clockgen node is not only IP block
> Node but also a clock provider node

I don't understand why that merits lumping them together.

Just describe them separately.

> At first, I want to add a extra fixed-clock node and move the clock-frequency of clockgen 
> Node to it, but it is against the backward compatibility

Right.

> which I think it is not a big deal, Because nobody hasn't used it yet.

The point is it will require updating U-Boot to use it, versus existing
U-Boots which already patch up the clock-frequency in the clockgen node.
And there's nothing semantically wrong with the way it currently is.

> If I add a extra node with the clock-frequency property and don't move the
> clock-frequency property of clockgen, that would be redundant because both clockgen node
> and the extra node have the same clock-frequency node.
> So, I choose what I did now.

I'm not complaining about how you structured the nodes, just how you
documented them.

-Scott
tang yuantian - Sept. 17, 2013, 7:19 a.m.
> > > On Wed, 2013-09-11 at 20:31 -0500, Tang Yuantian-B29983 wrote:

> > > > > -----Original Message-----

> > > > > From: Wood Scott-B07421

> > > > > Sent: 2013年9月12日 星期四 9:10

> > > > > To: Tang Yuantian-B29983

> > > > > Cc: galak@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;

> > > > > devicetree@vger.kernel.org; Li Yang-Leo-R58472

> > > > > Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device

> > > > > tree nodes

> > > > >

> > > > > This description of "reg" is overly specific (assumes how the

> > > > > parent node's ranges are set up), incomplete (there's a size as

> > > > > well as the offset), and does not apply to the clockgen node

> > > > > itself (you probably shouldn't lump them together like this).

> > > > >

> > > > Do you mean I should explain the REG of clockgen and its child

> > > > node

> > > respectively?

> > > >

> > > > > > +- clocks : shall be the input parent clock phandle for the

> clock.

> > > > >

> > > > > Not required on the clockgen node

> > > > >

> > > > Required by child node of clockgen.

> > >

> > > My point is that you're lumping several different types of nodes

> > > together with one binding, when some parts of the binding are not

> > > applicable to the clockgen node.

> > >

> > Not several, just two types of nodes.

> > One is clockgen node, the other is PLL and mux nodes.

> 

> clockgen + PLL + mux = 3 = several :-)

> 

> > The reason they lumped together is that the clockgen node is not only

> > IP block Node but also a clock provider node

> 

> I don't understand why that merits lumping them together.

> 

> Just describe them separately.

> 

It is not that easy to separate them because clockgen node plays two types
Of roles. Take REG property as example:
As IP block node, REG should be reg = <0xe1000 0x1000>, while as
Clock provider node, it should be reg = <0xabc 0x4> or no reg at all(for fixed clock).

> > At first, I want to add a extra fixed-clock node and move the

> > clock-frequency of clockgen Node to it, but it is against the backward

> > compatibility

> 

> Right.

> 

> > which I think it is not a big deal, Because nobody hasn't used it yet.

> 

> The point is it will require updating U-Boot to use it, versus existing

> U-Boots which already patch up the clock-frequency in the clockgen node.

> And there's nothing semantically wrong with the way it currently is.

> 

Yes, nothing wrong about it.
But we will keep adding the clockgen-x.y node all the time in uboot.
If we have one extra node to keep clock-frequency, it would be updated only once.

> > If I add a extra node with the clock-frequency property and don't move

> > the clock-frequency property of clockgen, that would be redundant

> > because both clockgen node and the extra node have the same clock-

> frequency node.

> > So, I choose what I did now.

> 

> I'm not complaining about how you structured the nodes, just how you

> documented them.

> 

As I said it is hard to document clockgen node if we don't separate its
two roles.
I think the following structure is better.

+   clockgen: global-utilities@e1000 {
+       compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+       reg = <0xe1000 0x1000>;
+       #address-cells = <1>;
+       #size-cells = <1>;
	  
	  Sysclk:sysclk {
	  	compatible = "fsl,qoriq-sysclk", "fixed-clock";
       	clock-output-names = "sysclk";
       	#clock-cells = <0>;   
		clock-frequency = <0>;		
	  }
+       pll0: pll0@800 {
+           #clock-cells = <1>;
+           reg = <0x800 0x4>;
+           compatible = "fsl,qoriq-chassis1-core-pll";
+           clocks = <& Sysclk >;
+           clock-output-names = "pll0", "pll0-div2";
+       };

Regards,
Yuantian

> -Scott

>

Patch

diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt b/Documentation/devicetree/bindings/clock/corenet-clock.txt
new file mode 100644
index 0000000..51eab75
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt
@@ -0,0 +1,80 @@ 
+Device Tree Clock bindings for Freescale PowerPC corenet platform
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one or more of the following:
+	- "fsl,<chip>-clockgen": for chip specific clock block
+	- "fsl,qoriq-clockgen-[1,2].0": for chassis 1.0 and 2.0 clock
+		block respectively.
+	- "fsl,qoriq-chassis[1,2]-core-pll" - for a core PLL clock
+	- "fsl,qoriq-chassis[1,2]-core-mux" - for a core multiplexer clock.
+		Divided from the core PLL clock
+	- "fixed-clock" - from common clock binding; should be output clock
+		of oscillator
+- reg : shall be the control register offset from clock block base address.
+- clocks : shall be the input parent clock phandle for the clock.
+- #clock-cells : from common clock binding; shall be set to 0 or 1.
+- clock-names : from common clock binding
+- clock-output-names : from common clock binding
+
+Example for clock provider:
+
+/ {
+	clockgen: global-utilities@e1000 {
+		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0",
+				   "fixed-clock";
+		reg = <0xe1000 0x1000>;
+		clock-frequency = <0>;
+		clock-output-names = "sysclk";
+		#clock-cells = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pll0: pll0@800 {
+			#clock-cells = <1>;
+			reg = <0x800 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll0", "pll0-div2";
+		};
+
+		pll1: pll1@820 {
+			#clock-cells = <1>;
+			reg = <0x820 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll1", "pll1-div2";
+		};
+
+		mux0: mux0@0 {
+			#clock-cells = <0>;
+			reg = <0x0 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux0";
+		};
+
+		mux1: mux1@20 {
+			#clock-cells = <0>;
+			reg = <0x20 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux1";
+		};
+	};
+  }
+
+Example for clock consumer:
+
+/ {
+	cpu0: PowerPC,e5500@0 {
+		...
+		clocks = <&mux0>;
+		...
+	};
+  }
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 5a6615d..69e651e 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -85,7 +85,39 @@ 
 	};
 
 	clockgen: global-utilities@e1000 {
-		compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
+		compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0",
+				   "fixed-clock";
+		clock-output-names = "sysclk";
+		#clock-cells = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pll0: pll0@800 {
+			#clock-cells = <1>;
+			reg = <0x800 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+		};
+
+		pll1: pll1@820 {
+			#clock-cells = <1>;
+			reg = <0x820 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+		};
+
+		mux0: mux0@0 {
+			#clock-cells = <0>;
+			reg = <0x0 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
+			clock-names = "pll0_0", "pll0_1", "pll0_2",
+				"pll1_0", "pll1_1", "pll1_2";
+			clock-output-names = "cmux0";
+		};
 	};
 
 	rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 7b4426e..a11126b 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -62,11 +62,13 @@ 
 		cpu0: PowerPC,e6500@0 {
 			device_type = "cpu";
 			reg = <0 1>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2>;
 		};
 		cpu1: PowerPC,e6500@2 {
 			device_type = "cpu";
 			reg = <2 3>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2>;
 		};
 	};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index e5cf6c8..6fa242f 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -129,7 +129,39 @@ 
 	};
 
 	clockgen: global-utilities@e1000 {
-		compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
+		compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0",
+				   "fixed-clock";
+		clock-output-names = "sysclk";
+		#clock-cells = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pll0: pll0@800 {
+			#clock-cells = <1>;
+			reg = <0x800 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+		};
+
+		pll1: pll1@820 {
+			#clock-cells = <1>;
+			reg = <0x820 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+		};
+
+		mux0: mux0@0 {
+			#clock-cells = <0>;
+			reg = <0x0 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
+			clock-names = "pll0_0", "pll0_1", "pll0_2",
+				"pll1_0", "pll1_1", "pll1_2";
+			clock-output-names = "cmux0";
+		};
 	};
 
 	rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 5263fa4..185a231 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -62,21 +62,25 @@ 
 		cpu0: PowerPC,e6500@0 {
 			device_type = "cpu";
 			reg = <0 1>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2>;
 		};
 		cpu1: PowerPC,e6500@2 {
 			device_type = "cpu";
 			reg = <2 3>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2>;
 		};
 		cpu2: PowerPC,e6500@4 {
 			device_type = "cpu";
 			reg = <4 5>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2>;
 		};
 		cpu3: PowerPC,e6500@6 {
 			device_type = "cpu";
 			reg = <6 7>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2>;
 		};
 	};
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index dc6cc5a..358c36d 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -305,9 +305,66 @@ 
 	};
 
 	clockgen: global-utilities@e1000 {
-		compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
+		compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0",
+				   "fixed-clock";
 		reg = <0xe1000 0x1000>;
 		clock-frequency = <0>;
+		clock-output-names = "sysclk";
+		#clock-cells = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pll0: pll0@800 {
+			#clock-cells = <1>;
+			reg = <0x800 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll0", "pll0-div2";
+		};
+
+		pll1: pll1@820 {
+			#clock-cells = <1>;
+			reg = <0x820 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll1", "pll1-div2";
+		};
+
+		mux0: mux0@0 {
+			#clock-cells = <0>;
+			reg = <0x0 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux0";
+		};
+
+		mux1: mux1@20 {
+			#clock-cells = <0>;
+			reg = <0x20 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux1";
+		};
+
+		mux2: mux2@40 {
+			#clock-cells = <0>;
+			reg = <0x40 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux2";
+		};
+
+		mux3: mux3@60 {
+			#clock-cells = <0>;
+			reg = <0x60 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux3";
+		};
 	};
 
 	rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
index 7a2697d..22f3b14 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -81,6 +81,7 @@ 
 		cpu0: PowerPC,e500mc@0 {
 			device_type = "cpu";
 			reg = <0>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2_0>;
 			L2_0: l2-cache {
 				next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@ 
 		cpu1: PowerPC,e500mc@1 {
 			device_type = "cpu";
 			reg = <1>;
+			clocks = <&mux1>;
 			next-level-cache = <&L2_1>;
 			L2_1: l2-cache {
 				next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@ 
 		cpu2: PowerPC,e500mc@2 {
 			device_type = "cpu";
 			reg = <2>;
+			clocks = <&mux2>;
 			next-level-cache = <&L2_2>;
 			L2_2: l2-cache {
 				next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@ 
 		cpu3: PowerPC,e500mc@3 {
 			device_type = "cpu";
 			reg = <3>;
+			clocks = <&mux3>;
 			next-level-cache = <&L2_3>;
 			L2_3: l2-cache {
 				next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 3fa1e22..87030ce 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -332,9 +332,66 @@ 
 	};
 
 	clockgen: global-utilities@e1000 {
-		compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
+		compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0",
+				   "fixed-clock";
 		reg = <0xe1000 0x1000>;
 		clock-frequency = <0>;
+		clock-output-names = "sysclk";
+		#clock-cells = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pll0: pll0@800 {
+			#clock-cells = <1>;
+			reg = <0x800 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll0", "pll0-div2";
+		};
+
+		pll1: pll1@820 {
+			#clock-cells = <1>;
+			reg = <0x820 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll1", "pll1-div2";
+		};
+
+		mux0: mux0@0 {
+			#clock-cells = <0>;
+			reg = <0x0 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux0";
+		};
+
+		mux1: mux1@20 {
+			#clock-cells = <0>;
+			reg = <0x20 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux1";
+		};
+
+		mux2: mux2@40 {
+			#clock-cells = <0>;
+			reg = <0x40 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux2";
+		};
+
+		mux3: mux3@60 {
+			#clock-cells = <0>;
+			reg = <0x60 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux3";
+		};
 	};
 
 	rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
index c9ca2c3..468e8be 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -82,6 +82,7 @@ 
 		cpu0: PowerPC,e500mc@0 {
 			device_type = "cpu";
 			reg = <0>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2_0>;
 			L2_0: l2-cache {
 				next-level-cache = <&cpc>;
@@ -90,6 +91,7 @@ 
 		cpu1: PowerPC,e500mc@1 {
 			device_type = "cpu";
 			reg = <1>;
+			clocks = <&mux1>;
 			next-level-cache = <&L2_1>;
 			L2_1: l2-cache {
 				next-level-cache = <&cpc>;
@@ -98,6 +100,7 @@ 
 		cpu2: PowerPC,e500mc@2 {
 			device_type = "cpu";
 			reg = <2>;
+			clocks = <&mux2>;
 			next-level-cache = <&L2_2>;
 			L2_2: l2-cache {
 				next-level-cache = <&cpc>;
@@ -106,6 +109,7 @@ 
 		cpu3: PowerPC,e500mc@3 {
 			device_type = "cpu";
 			reg = <3>;
+			clocks = <&mux3>;
 			next-level-cache = <&L2_3>;
 			L2_3: l2-cache {
 				next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 34769a7..7ecefb3 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -352,9 +352,118 @@ 
 	};
 
 	clockgen: global-utilities@e1000 {
-		compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
+		compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0",
+				   "fixed-clock";
 		reg = <0xe1000 0x1000>;
 		clock-frequency = <0>;
+		clock-output-names = "sysclk";
+		#clock-cells = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pll0: pll0@800 {
+			#clock-cells = <1>;
+			reg = <0x800 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll0", "pll0-div2";
+		};
+
+		pll1: pll1@820 {
+			#clock-cells = <1>;
+			reg = <0x820 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll1", "pll1-div2";
+		};
+
+		pll2: pll2@840 {
+			#clock-cells = <1>;
+			reg = <0x840 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll2", "pll2-div2";
+		};
+
+		pll3: pll3@860 {
+			#clock-cells = <1>;
+			reg = <0x860 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll3", "pll3-div2";
+		};
+
+		mux0: mux0@0 {
+			#clock-cells = <0>;
+			reg = <0x0 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux0";
+		};
+
+		mux1: mux1@20 {
+			#clock-cells = <0>;
+			reg = <0x20 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux1";
+		};
+
+		mux2: mux2@40 {
+			#clock-cells = <0>;
+			reg = <0x40 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux2";
+		};
+
+		mux3: mux3@60 {
+			#clock-cells = <0>;
+			reg = <0x60 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux3";
+		};
+
+		mux4: mux4@80 {
+			#clock-cells = <0>;
+			reg = <0x80 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+			clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1";
+			clock-output-names = "cmux4";
+		};
+
+		mux5: mux5@a0 {
+			#clock-cells = <0>;
+			reg = <0xa0 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+			clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1";
+			clock-output-names = "cmux5";
+		};
+
+		mux6: mux6@c0 {
+			#clock-cells = <0>;
+			reg = <0xc0 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+			clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1";
+			clock-output-names = "cmux6";
+		};
+
+		mux7: mux7@e0 {
+			#clock-cells = <0>;
+			reg = <0xe0 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+			clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1";
+			clock-output-names = "cmux7";
+		};
 	};
 
 	rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
index 493d9a0..0040b5a 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -81,6 +81,7 @@ 
 		cpu0: PowerPC,e500mc@0 {
 			device_type = "cpu";
 			reg = <0>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2_0>;
 			L2_0: l2-cache {
 				next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@ 
 		cpu1: PowerPC,e500mc@1 {
 			device_type = "cpu";
 			reg = <1>;
+			clocks = <&mux1>;
 			next-level-cache = <&L2_1>;
 			L2_1: l2-cache {
 				next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@ 
 		cpu2: PowerPC,e500mc@2 {
 			device_type = "cpu";
 			reg = <2>;
+			clocks = <&mux2>;
 			next-level-cache = <&L2_2>;
 			L2_2: l2-cache {
 				next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@ 
 		cpu3: PowerPC,e500mc@3 {
 			device_type = "cpu";
 			reg = <3>;
+			clocks = <&mux3>;
 			next-level-cache = <&L2_3>;
 			L2_3: l2-cache {
 				next-level-cache = <&cpc>;
@@ -113,6 +117,7 @@ 
 		cpu4: PowerPC,e500mc@4 {
 			device_type = "cpu";
 			reg = <4>;
+			clocks = <&mux4>;
 			next-level-cache = <&L2_4>;
 			L2_4: l2-cache {
 				next-level-cache = <&cpc>;
@@ -121,6 +126,7 @@ 
 		cpu5: PowerPC,e500mc@5 {
 			device_type = "cpu";
 			reg = <5>;
+			clocks = <&mux5>;
 			next-level-cache = <&L2_5>;
 			L2_5: l2-cache {
 				next-level-cache = <&cpc>;
@@ -129,6 +135,7 @@ 
 		cpu6: PowerPC,e500mc@6 {
 			device_type = "cpu";
 			reg = <6>;
+			clocks = <&mux6>;
 			next-level-cache = <&L2_6>;
 			L2_6: l2-cache {
 				next-level-cache = <&cpc>;
@@ -137,6 +144,7 @@ 
 		cpu7: PowerPC,e500mc@7 {
 			device_type = "cpu";
 			reg = <7>;
+			clocks = <&mux7>;
 			next-level-cache = <&L2_7>;
 			L2_7: l2-cache {
 				next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index bc3ae5a..3044089 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -337,9 +337,48 @@ 
 	};
 
 	clockgen: global-utilities@e1000 {
-		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0",
+				   "fixed-clock";
 		reg = <0xe1000 0x1000>;
 		clock-frequency = <0>;
+		clock-output-names = "sysclk";
+		#clock-cells = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pll0: pll0@800 {
+			#clock-cells = <1>;
+			reg = <0x800 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll0", "pll0-div2";
+		};
+
+		pll1: pll1@820 {
+			#clock-cells = <1>;
+			reg = <0x820 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll1", "pll1-div2";
+		};
+
+		mux0: mux0@0 {
+			#clock-cells = <0>;
+			reg = <0x0 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux0";
+		};
+
+		mux1: mux1@20 {
+			#clock-cells = <0>;
+			reg = <0x20 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux1";
+		};
 	};
 
 	rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index 8df47fc..fe1a2e6 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -88,6 +88,7 @@ 
 		cpu0: PowerPC,e5500@0 {
 			device_type = "cpu";
 			reg = <0>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2_0>;
 			L2_0: l2-cache {
 				next-level-cache = <&cpc>;
@@ -96,6 +97,7 @@ 
 		cpu1: PowerPC,e5500@1 {
 			device_type = "cpu";
 			reg = <1>;
+			clocks = <&mux1>;
 			next-level-cache = <&L2_1>;
 			L2_1: l2-cache {
 				next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index a91897f..682787b 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -297,9 +297,66 @@ 
 	};
 
 	clockgen: global-utilities@e1000 {
-		compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
+		compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0",
+				   "fixed-clock";
 		reg = <0xe1000 0x1000>;
 		clock-frequency = <0>;
+		clock-output-names = "sysclk";
+		#clock-cells = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pll0: pll0@800 {
+			#clock-cells = <1>;
+			reg = <0x800 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll0", "pll0-div2";
+		};
+
+		pll1: pll1@820 {
+			#clock-cells = <1>;
+			reg = <0x820 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll1", "pll1-div2";
+		};
+
+		mux0: mux0@0 {
+			#clock-cells = <0>;
+			reg = <0x0 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux0";
+		};
+
+		mux1: mux1@20 {
+			#clock-cells = <0>;
+			reg = <0x20 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux1";
+		};
+
+		mux2: mux2@40 {
+			#clock-cells = <0>;
+			reg = <0x40 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux2";
+		};
+
+		mux3: mux3@60 {
+			#clock-cells = <0>;
+			reg = <0x60 0x4>;
+			compatible = "fsl,qoriq-chassis1-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+			clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+			clock-output-names = "cmux3";
+		};
 	};
 
 	rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
index 40ca943..3674686 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -81,6 +81,7 @@ 
 		cpu0: PowerPC,e5500@0 {
 			device_type = "cpu";
 			reg = <0>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2_0>;
 			L2_0: l2-cache {
 				next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@ 
 		cpu1: PowerPC,e5500@1 {
 			device_type = "cpu";
 			reg = <1>;
+			clocks = <&mux1>;
 			next-level-cache = <&L2_1>;
 			L2_1: l2-cache {
 				next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@ 
 		cpu2: PowerPC,e5500@2 {
 			device_type = "cpu";
 			reg = <2>;
+			clocks = <&mux2>;
 			next-level-cache = <&L2_2>;
 			L2_2: l2-cache {
 				next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@ 
 		cpu3: PowerPC,e5500@3 {
 			device_type = "cpu";
 			reg = <3>;
+			clocks = <&mux3>;
 			next-level-cache = <&L2_3>;
 			L2_3: l2-cache {
 				next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index bd611a9..b90a8c6 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -368,8 +368,90 @@ 
 	};
 
 	clockgen: global-utilities@e1000 {
-		compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
+		compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0",
+				   "fixed-clock";
 		reg = <0xe1000 0x1000>;
+		clock-output-names = "sysclk";
+		#clock-cells = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pll0: pll0@800 {
+			#clock-cells = <1>;
+			reg = <0x800 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+		};
+
+		pll1: pll1@820 {
+			#clock-cells = <1>;
+			reg = <0x820 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+		};
+
+		pll2: pll2@840 {
+			#clock-cells = <1>;
+			reg = <0x840 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll2", "pll2-div2", "pll2-div4";
+		};
+
+		pll3: pll3@860 {
+			#clock-cells = <1>;
+			reg = <0x860 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll3", "pll3-div2", "pll3-div4";
+		};
+
+		pll4: pll4@880 {
+			#clock-cells = <1>;
+			reg = <0x880 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-pll";
+			clocks = <&clockgen>;
+			clock-output-names = "pll4", "pll4-div2", "pll4-div4";
+		};
+
+		mux0: mux0@0 {
+			#clock-cells = <0>;
+			reg = <0x0 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+				 <&pll1 0>, <&pll1 1>, <&pll1 2>,
+				 <&pll2 0>, <&pll2 1>, <&pll2 2>;
+			clock-names = "pll0_0", "pll0_1", "pll0_2",
+				"pll1_0", "pll1_1", "pll1_2",
+				"pll2_0", "pll2_1", "pll2_2";
+			clock-output-names = "cmux0";
+		};
+
+		mux1: mux1@20 {
+			#clock-cells = <0>;
+			reg = <0x20 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+				 <&pll1 0>, <&pll1 1>, <&pll1 2>,
+				 <&pll2 0>, <&pll2 1>, <&pll2 2>;
+			clock-names = "pll0_0", "pll0_1", "pll0_2",
+				"pll1_0", "pll1_1", "pll1_2",
+				"pll2_0", "pll2_1", "pll2_2";
+			clock-output-names = "cmux1";
+		};
+
+		mux2: mux2@40 {
+			#clock-cells = <0>;
+			reg = <0x40 0x4>;
+			compatible = "fsl,qoriq-chassis2-core-mux";
+			clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>,
+				 <&pll4 0>, <&pll4 1>, <&pll4 2>;
+			clock-names = "pll3_0", "pll3_1", "pll3_2",
+				"pll4_0", "pll4_1", "pll4_2";
+			clock-output-names = "cmux2";
+		};
 	};
 
 	rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index a93c55a..0b8ccc5 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -67,61 +67,73 @@ 
 		cpu0: PowerPC,e6500@0 {
 			device_type = "cpu";
 			reg = <0 1>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2_1>;
 		};
 		cpu1: PowerPC,e6500@2 {
 			device_type = "cpu";
 			reg = <2 3>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2_1>;
 		};
 		cpu2: PowerPC,e6500@4 {
 			device_type = "cpu";
 			reg = <4 5>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2_1>;
 		};
 		cpu3: PowerPC,e6500@6 {
 			device_type = "cpu";
 			reg = <6 7>;
+			clocks = <&mux0>;
 			next-level-cache = <&L2_1>;
 		};
 		cpu4: PowerPC,e6500@8 {
 			device_type = "cpu";
 			reg = <8 9>;
+			clocks = <&mux1>;
 			next-level-cache = <&L2_2>;
 		};
 		cpu5: PowerPC,e6500@10 {
 			device_type = "cpu";
 			reg = <10 11>;
+			clocks = <&mux1>;
 			next-level-cache = <&L2_2>;
 		};
 		cpu6: PowerPC,e6500@12 {
 			device_type = "cpu";
 			reg = <12 13>;
+			clocks = <&mux1>;
 			next-level-cache = <&L2_2>;
 		};
 		cpu7: PowerPC,e6500@14 {
 			device_type = "cpu";
 			reg = <14 15>;
+			clocks = <&mux1>;
 			next-level-cache = <&L2_2>;
 		};
 		cpu8: PowerPC,e6500@16 {
 			device_type = "cpu";
 			reg = <16 17>;
+			clocks = <&mux2>;
 			next-level-cache = <&L2_3>;
 		};
 		cpu9: PowerPC,e6500@18 {
 			device_type = "cpu";
 			reg = <18 19>;
+			clocks = <&mux2>;
 			next-level-cache = <&L2_3>;
 		};
 		cpu10: PowerPC,e6500@20 {
 			device_type = "cpu";
 			reg = <20 21>;
+			clocks = <&mux2>;
 			next-level-cache = <&L2_3>;
 		};
 		cpu11: PowerPC,e6500@22 {
 			device_type = "cpu";
 			reg = <22 23>;
+			clocks = <&mux2>;
 			next-level-cache = <&L2_3>;
 		};
 	};