From patchwork Wed Sep 11 05:56:43 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dongsheng Wang X-Patchwork-Id: 274121 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 2DA822C0771 for ; Wed, 11 Sep 2013 16:03:04 +1000 (EST) Received: from db8outboundpool.messaging.microsoft.com (mail-db8lp0186.outbound.messaging.microsoft.com [213.199.154.186]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "MSIT Machine Auth CA 2" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 9DFFC2C03C6 for ; Wed, 11 Sep 2013 16:00:49 +1000 (EST) Received: from mail17-db8-R.bigfish.com (10.174.8.254) by DB8EHSOBE017.bigfish.com (10.174.4.80) with Microsoft SMTP Server id 14.1.225.22; Wed, 11 Sep 2013 06:00:43 +0000 Received: from mail17-db8 (localhost [127.0.0.1]) by mail17-db8-R.bigfish.com (Postfix) with ESMTP id D4193B40217; Wed, 11 Sep 2013 06:00:43 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h1de097h8275bhz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h1155h) Received: from mail17-db8 (localhost.localdomain [127.0.0.1]) by mail17-db8 (MessageSwitch) id 1378879241421959_13733; Wed, 11 Sep 2013 06:00:41 +0000 (UTC) Received: from DB8EHSMHS006.bigfish.com (unknown [10.174.8.251]) by mail17-db8.bigfish.com (Postfix) with ESMTP id 58514240041; Wed, 11 Sep 2013 06:00:41 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS006.bigfish.com (10.174.4.16) with Microsoft SMTP Server (TLS) id 14.16.227.3; Wed, 11 Sep 2013 06:00:41 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.3.158.2; Wed, 11 Sep 2013 06:00:39 +0000 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r8B60RRg023128; Tue, 10 Sep 2013 23:00:37 -0700 From: Dongsheng Wang To: Subject: [PATCH v3 3/4] powerpc/85xx: add hardware automatically enter pw20 state Date: Wed, 11 Sep 2013 13:56:43 +0800 Message-ID: <1378879004-2446-3-git-send-email-dongsheng.wang@freescale.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1378879004-2446-1-git-send-email-dongsheng.wang@freescale.com> References: <1378879004-2446-1-git-send-email-dongsheng.wang@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: linuxppc-dev@lists.ozlabs.org, Wang Dongsheng X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.16rc2 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Wang Dongsheng Using hardware features make core automatically enter PW20 state. Set a TB count to hardware, the effective count begins when PW10 is entered. When the effective period has expired, the core will proceed from PW10 to PW20 if no exit conditions have occurred during the period. Signed-off-by: Wang Dongsheng --- *v3: Assembly code instead of C code. *v2: Remove: delete setup_idle_hw_governor function. delete "Fix erratum" for rev1. Move: move setup_* into __setup/restore_cpu_e6500. arch/powerpc/kernel/cpu_setup_fsl_booke.S | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) -- 1.8.0 diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 3c03c109..7389d49 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -54,6 +54,27 @@ _GLOBAL(__e500_dcache_setup) blr /* + * FIXME - We don't know, what time should we let the core into PW20 state. + * because we don't know the current state of the cpu load. And threads are + * independent, so we can not know the state of different thread has been + * idle. + */ +#define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */ +_GLOBAL(setup_pw20_idle) + mfspr r3, SPRN_PWRMGTCR0 + + /* Set PW20_WAIT bit, enable pw20 state*/ + ori r3, r3, PWRMGTCR0_PW20_WAIT + li r4, PW20_WAIT_IDLE_BIT + + /* Set Automatic PW20 Core Idle Count */ + rlwimi r3, r4, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT + + mtspr SPRN_PWRMGTCR0, r3 + + blr + +/* * FIXME - We don't know the AltiVec application scenarios. */ #define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */ @@ -76,6 +97,7 @@ _GLOBAL(__setup_cpu_e6500) #ifdef CONFIG_PPC64 bl .setup_altivec_ivors #endif + bl .setup_pw20_idle bl .setup_altivec_idle bl __setup_cpu_e5500 mtlr r6 @@ -138,6 +160,7 @@ _GLOBAL(__setup_cpu_e5500) _GLOBAL(__restore_cpu_e6500) mflr r5 bl .setup_altivec_ivors + bl .setup_pw20_idle bl .setup_altivec_idle bl __restore_cpu_e5500 mtlr r5