From patchwork Tue Sep 10 09:12:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo Serra X-Patchwork-Id: 273788 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5E7C02C0198 for ; Tue, 10 Sep 2013 19:19:41 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 141B34A061; Tue, 10 Sep 2013 11:19:40 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id E7zn2E4YP1gz; Tue, 10 Sep 2013 11:19:39 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D251B4A062; Tue, 10 Sep 2013 11:19:35 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D82E24A062 for ; Tue, 10 Sep 2013 11:19:29 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pXPFoGgxA+oy for ; Tue, 10 Sep 2013 11:19:24 +0200 (CEST) X-Greylist: delayed 371 seconds by postgrey-1.27 at theia; Tue, 10 Sep 2013 11:19:18 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ee0-f44.google.com (mail-ee0-f44.google.com [74.125.83.44]) by theia.denx.de (Postfix) with ESMTPS id 1604F4A061 for ; Tue, 10 Sep 2013 11:19:18 +0200 (CEST) Received: by mail-ee0-f44.google.com with SMTP id b47so3737694eek.31 for ; Tue, 10 Sep 2013 02:19:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=QVFeF8yV15vdgLWLj8NQZqhv6sRUzWSbDlVRhqS1CVM=; b=U0th0gWe+fR+5nn52r+4kky/c74CGNjeytP1O15W/DYeG3d7fis0KHZb9TvURNJWwP RdWg6L8I2CXZQcIVbMSr3DLZKyJyp3jVms3Pf8jw0dw2qKlmlTdhVLUdjB8yS7QDuf2r SwgH2cO4BSpAjPiSvadIAyI6PouuavK0YPf65sHPYjMWvRh4o6oklqouEgZxHhxjI1sV FkEAtkOmKqTkyOeOpR37dM8DOTTNzs8vcuIpsmt/SYB6Awu4e4OU+nyO/GZJqAzRYQff TWbWbj3I9sKB9AsrZB2GTjyKOaNDMLKSB2b0TGo1m8u/cgGr8E0yrl6jQZiQz5sAKMN7 oZkw== X-Received: by 10.14.127.137 with SMTP id d9mr57221eei.90.1378804382634; Tue, 10 Sep 2013 02:13:02 -0700 (PDT) Received: from localhost.localdomain (43.Red-2-139-180.staticIP.rima-tde.net. [2.139.180.43]) by mx.google.com with ESMTPSA id x47sm29614059eea.16.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 10 Sep 2013 02:13:01 -0700 (PDT) From: Enric Balletbo i Serra To: Date: Tue, 10 Sep 2013 11:12:26 +0200 Message-Id: <1378804346-15252-1-git-send-email-eballetbo@gmail.com> X-Mailer: git-send-email 1.8.1.2 Cc: trini@ti.com, Enric Balletbo i Serra Subject: [U-Boot] [PATCH] ARM: IGEP0033: Update timing to run DDR at 400MHz. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Enric Balletbo i Serra We can run the DDR at 400MHz, so update the timings for that purpose. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Javier Martinez Canillas --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 24 ++++++++++++------------ board/isee/igep0033/board.c | 4 ++-- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 95f7a9a..fe48b5f 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -110,20 +110,20 @@ #define MT41J512M8RH125_IOCTRL_VALUE 0x18B /* Samsung K4B2G1646E-BIH9 */ -#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06 -#define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B -#define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A -#define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F -#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2 -#define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B +#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x07 +#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B +#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA +#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF +#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2 +#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 #define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1 -#define K4B2G1646EBIH9_RATIO 0x40 -#define K4B2G1646EBIH9_INVERT_CLKOUT 0x1 -#define K4B2G1646EBIH9_RD_DQS 0x3B -#define K4B2G1646EBIH9_WR_DQS 0x85 -#define K4B2G1646EBIH9_PHY_FIFO_WE 0x100 -#define K4B2G1646EBIH9_PHY_WR_DATA 0xC1 +#define K4B2G1646EBIH9_RATIO 0x80 +#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0 +#define K4B2G1646EBIH9_RD_DQS 0x35 +#define K4B2G1646EBIH9_WR_DQS 0x3A +#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97 +#define K4B2G1646EBIH9_PHY_WR_DATA 0x76 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B /** diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 9e91f68..a9c34c6 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -64,7 +64,7 @@ static struct emif_regs ddr3_emif_reg_data = { #define OSC (V_OSCK/1000000) const struct dpll_params dpll_ddr = { - 303, OSC-1, 1, -1, -1, -1, -1}; + 400, OSC-1, 1, -1, -1, -1, -1}; const struct dpll_params *get_dpll_ddr_params(void) { @@ -83,7 +83,7 @@ void set_mux_conf_regs(void) void sdram_init(void) { - config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data, + config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } #endif