Patchwork [U-Boot,v2,3/3] am335x: update README for BCH16

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Submitter pekon gupta
Date Sept. 10, 2013, 7:25 a.m.
Message ID <1378797908-22567-4-git-send-email-pekon@ti.com>
Download mbox | patch
Permalink /patch/273771/
State Superseded
Delegated to: Scott Wood
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Comments

pekon gupta - Sept. 10, 2013, 7:25 a.m.
Adds explanation on how to select ECC scheme.

Signed-off-by: Pekon Gupta <pekon@ti.com>
---
 board/ti/am335x/README | 43 +++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 41 insertions(+), 2 deletions(-)

Patch

diff --git a/board/ti/am335x/README b/board/ti/am335x/README
index 941dfbb..05e53b1 100644
--- a/board/ti/am335x/README
+++ b/board/ti/am335x/README
@@ -30,12 +30,13 @@  Step-1: Building u-boot for NAND boot
 	CONFIG_SYS_NAND_BLOCK_SIZE	number of bytes in NAND erase-block
 	CONFIG_SYS_NAND_ECCPOS		ECC map for NAND page
 	CONFIG_SYS_NAND_ECCSCHEME	ECC scheme used by NAND
-					0 - HAM1_SW
-					1 - HAM1_HW
+					0 - HAM1_SW  (for legacy devices)
+					1 - HAM1_HW  (for legacy devices)
 					2 - BCH4_SW  (unsupported)
 					3 - BCH4_HW  (unsupported)
 					4 - BCH8_SW
 					5 - BCH8_HW
+					6 - BCH16_HW
 
 Step-2: Flashing NAND via MMC/SD
 	# select BOOTSEL to MMC/SD boot and boot from MMC/SD card
@@ -63,6 +64,44 @@  Step-2: Flashing NAND via MMC/SD
 Step-3: Set BOOTSEL pin to select NAND boot, and POR the device.
 	The device should boot from images flashed on NAND device.
 
+
+How to select ECC scheme ?
+--------------------------
+Though higher ECC schemes have more capability to detect and correct
+bit-flips, but still selection of ECC scheme is dependent on following
+- hardware engines present in SoC.
+	Some legacy OMAP SoC do not have ELM h/w engine thus such
+	SoC cannot support BCHx_HW ECC schemes.
+- size of OOB/Spare region
+	With higher ECC schemes, more OOB/Spare area is required to
+	store ECC. So choice of ECC scheme is limited by NAND oobsize.
+
+In general following expression can help:
+	NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
+where
+	NAND_OOBSIZE	= number of bytes available in
+			OOB/spare area per NAND page.
+	NAND_PAGESIZE	= bytes in main-area of NAND page.
+	ECC_BYTES	= number of ECC bytes generated to
+			protect 512 bytes of data, which is:
+			3 for HAM1_xx ecc schemes
+			7 for BCH4_xx ecc schemes
+			14 for BCH8_xx ecc schemes
+			26 for BCH16_xx ecc schemes
+
+	example to check for BCH16 on 2K page NAND
+	NAND_PAGESIZE = 2048
+	NAND_OOBSIZE = 64
+	2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
+	Thus BCH16 cannot be supported on 2K page NAND.
+
+	However, for 4K pagesize NAND
+	NAND_PAGESIZE = 4096
+	NAND_OOBSIZE = 64
+	ECC_BYTES = 26
+	2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
+	Thus BCH16 can be supported on 4K page NAND.
+
 NOR
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