From patchwork Mon Sep 9 17:27:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 273622 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 001BF2C00A6 for ; Tue, 10 Sep 2013 03:28:49 +1000 (EST) Received: from localhost ([::1]:52932 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJ5Ga-00051v-1B for incoming@patchwork.ozlabs.org; Mon, 09 Sep 2013 13:28:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34657) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJ5Fy-0004oe-F1 for qemu-devel@nongnu.org; Mon, 09 Sep 2013 13:28:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VJ5Ft-0008T0-M9 for qemu-devel@nongnu.org; Mon, 09 Sep 2013 13:28:10 -0400 Received: from hall.aurel32.net ([2001:470:1f0b:4a8::1]:38644) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJ5Ft-0008Sw-EU for qemu-devel@nongnu.org; Mon, 09 Sep 2013 13:28:05 -0400 Received: from anguille.univ-lyon1.fr ([134.214.4.207] helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1VJ5Fs-0003kb-Gk; Mon, 09 Sep 2013 19:28:04 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.80) (envelope-from ) id 1VJ5Fm-0006eQ-NP; Mon, 09 Sep 2013 19:27:58 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 9 Sep 2013 19:27:48 +0200 Message-Id: <1378747670-25512-3-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1378747670-25512-1-git-send-email-aurelien@aurel32.net> References: <1378747670-25512-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f0b:4a8::1 Cc: Paolo Bonzini , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH v2 2/4] tcg/optimize: fix known-zero bits optimization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Known-zero bits optimization is a great idea that helps to generate more optimized code. However the current implementation only works in very few cases as the computed mask is not saved. Fix this to make it really working. Cc: Richard Henderson Cc: Paolo Bonzini Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- tcg/optimize.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index c539e39..0ed8983 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -695,7 +695,8 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, break; } - /* Simplify using known-zero bits */ + /* Simplify using known-zero bits. Currently only ops with a single + output argument is supported. */ mask = -1; affected = -1; switch (op) { @@ -1157,6 +1158,11 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, } else { for (i = 0; i < def->nb_oargs; i++) { reset_temp(args[i]); + /* Save the corresponding known-zero bits mask for the + first output argument (only one supported so far). */ + if (i == 0) { + temps[args[i]].mask = mask; + } } } for (i = 0; i < def->nb_args; i++) {