| Message ID | 1378732388-4508-6-git-send-email-wangyijing@huawei.com |
|---|---|
| State | Accepted |
| Headers | show |
On Mon, Sep 09, 2013 at 09:13:07PM +0800, Yijing Wang wrote: > The PCI core caches the "PCI-E Max Payload Size Supported" in > pci_dev->pcie_mpss, so use that instead of pcie_capability_read_dword(). > Also use pcie_set_readrq() instead of pcie_capability_clear_and_set_word() > to simplify code. > > Signed-off-by: Yijing Wang <wangyijing@huawei.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Sep 09, 2013 at 09:13:07PM +0800, Yijing Wang wrote: > The PCI core caches the "PCI-E Max Payload Size Supported" in > pci_dev->pcie_mpss, so use that instead of pcie_capability_read_dword(). > Also use pcie_set_readrq() instead of pcie_capability_clear_and_set_word() > to simplify code. > > Signed-off-by: Yijing Wang <wangyijing@huawei.com> Acked-by: Mark Einon <mark.einon@gmail.com> -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c index f73e58f..876881d 100644 --- a/drivers/staging/et131x/et131x.c +++ b/drivers/staging/et131x/et131x.c @@ -3605,17 +3605,10 @@ static int et131x_pci_init(struct et131x_adapter *adapter, goto err_out; } - /* Let's set up the PORT LOGIC Register. First we need to know what - * the max_payload_size is - */ - if (pcie_capability_read_word(pdev, PCI_EXP_DEVCAP, &max_payload)) { - dev_err(&pdev->dev, - "Could not read PCI config space for Max Payload Size\n"); - goto err_out; - } + /* Let's set up the PORT LOGIC Register. */ /* Program the Ack/Nak latency and replay timers */ - max_payload &= 0x07; + max_payload = pdev->pcie_mpss; if (max_payload < 2) { static const u16 acknak[2] = { 0x76, 0xD0 }; @@ -3645,8 +3638,7 @@ static int et131x_pci_init(struct et131x_adapter *adapter, } /* Change the max read size to 2k */ - if (pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL, - PCI_EXP_DEVCTL_READRQ, 0x4 << 12)) { + if (pcie_set_readrq(pdev, 2048)) { dev_err(&pdev->dev, "Couldn't change PCI config space for Max read size\n"); goto err_out;
The PCI core caches the "PCI-E Max Payload Size Supported" in pci_dev->pcie_mpss, so use that instead of pcie_capability_read_dword(). Also use pcie_set_readrq() instead of pcie_capability_clear_and_set_word() to simplify code. Signed-off-by: Yijing Wang <wangyijing@huawei.com> --- drivers/staging/et131x/et131x.c | 14 +++----------- 1 files changed, 3 insertions(+), 11 deletions(-)