From patchwork Mon Sep 9 01:00:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 273466 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from casper.infradead.org (unknown [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BF9A12C00F2 for ; Mon, 9 Sep 2013 11:01:08 +1000 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VIpqR-0002E5-AE; Mon, 09 Sep 2013 01:00:47 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VIpqP-0001bk-6x; Mon, 09 Sep 2013 01:00:45 +0000 Received: from mail-ye0-x22d.google.com ([2607:f8b0:4002:c04::22d]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VIpqL-0001aX-WA for linux-arm-kernel@lists.infradead.org; Mon, 09 Sep 2013 01:00:43 +0000 Received: by mail-ye0-f173.google.com with SMTP id m3so1802757yen.4 for ; Sun, 08 Sep 2013 18:00:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=la4q4xrxf5ZixrQ6af7BVCQ/o+E/XlbgGDsiRIyU8O4=; b=My0Pf7eT6R3Gbis0X8bD56xButwWuRCvO8MRz8IX38vE4ssv2XfGzeZhqGRvgrULED bZ3xeJseVLLyl5IPeGvysfNqgz/L923dvNwiFDUclRgMNA2Dh+NBUogKFazbOs5CJutg K0T2wZGZkidypG/hXaWYctGIA8JWKrEGi2CVrUwbAWWQ1IWNsqSHV+1//JajQnOe6zoX iw9fICMhACEnobZ4zaEnhYHp+vtv4G8zprJ82/v+EyudapCY6kmC0Yki9Z8ijO7uqVY8 lS5teKVbnoTxnTV+UZc7gNPRhcb//5HdKuj+yBaXxnbowU9QytIsFHFN0y4oXJhyxasL 49/w== X-Received: by 10.236.85.237 with SMTP id u73mr36352yhe.67.1378688419041; Sun, 08 Sep 2013 18:00:19 -0700 (PDT) Received: from localhost.localdomain ([177.194.42.63]) by mx.google.com with ESMTPSA id d26sm8764996yhk.21.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 08 Sep 2013 18:00:18 -0700 (PDT) From: Fabio Estevam To: shawn.guo@linaro.org Subject: [PATCH 1/2] ARM: dts: mx6: Add mx6solo support Date: Sun, 8 Sep 2013 22:00:07 -0300 Message-Id: <1378688408-8689-1-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.8.1.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130908_210042_142174_D5638D8B X-CRM114-Status: GOOD ( 14.86 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (festevam[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Fabio Estevam , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Fabio Estevam Allow booting a device tree kernel on mx6solo. Signed-off-by: Fabio Estevam --- arch/arm/boot/dts/imx6s.dtsi | 82 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/Kconfig | 4 +-- arch/arm/mach-imx/mach-imx6q.c | 3 +- 3 files changed, 86 insertions(+), 3 deletions(-) create mode 100644 arch/arm/boot/dts/imx6s.dtsi diff --git a/arch/arm/boot/dts/imx6s.dtsi b/arch/arm/boot/dts/imx6s.dtsi new file mode 100644 index 0000000..461f44c --- /dev/null +++ b/arch/arm/boot/dts/imx6s.dtsi @@ -0,0 +1,82 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include "imx6dl-pinfunc.h" +#include "imx6qdl.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + }; + + soc { + ocram: sram@00900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + clocks = <&clks 142>; + }; + + aips1: aips-bus@02000000 { + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6dl-iomuxc"; + }; + + pxp: pxp@020f0000 { + reg = <0x020f0000 0x4000>; + interrupts = <0 98 0x04>; + }; + + epdc: epdc@020f4000 { + reg = <0x020f4000 0x4000>; + interrupts = <0 97 0x04>; + }; + + lcdif: lcdif@020f8000 { + reg = <0x020f8000 0x4000>; + interrupts = <0 39 0x04>; + }; + }; + + aips2: aips-bus@02100000 { + i2c4: i2c@021f8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx1-i2c"; + reg = <0x021f8000 0x4000>; + interrupts = <0 35 0x04>; + status = "disabled"; + }; + }; + }; +}; + +&ldb { + clocks = <&clks 33>, <&clks 34>, + <&clks 39>, <&clks 40>, + <&clks 135>, <&clks 136>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", + "di0", "di1"; + + lvds-channel@0 { + crtcs = <&ipu1 0>, <&ipu1 1>; + }; + + lvds-channel@1 { + crtcs = <&ipu1 0>, <&ipu1 1>; + }; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 29a8af6..9d96be8 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -784,7 +784,7 @@ config SOC_IMX53 This enables support for Freescale i.MX53 processor. config SOC_IMX6Q - bool "i.MX6 Quad/DualLite support" + bool "i.MX6 Quad/DualLite/Solo support" select ARCH_HAS_CPUFREQ select ARCH_HAS_OPP select ARM_ERRATA_754322 @@ -809,7 +809,7 @@ config SOC_IMX6Q select PM_OPP if PM help - This enables support for Freescale i.MX6 Quad processor. + This enables support for Freescale i.MX6 Q/DL/S processors. config SOC_IMX6SL bool "i.MX6 SoloLite support" diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 85a1b51..3d22a6c 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -299,10 +299,11 @@ static void __init imx6q_timer_init(void) static const char *imx6q_dt_compat[] __initdata = { "fsl,imx6dl", "fsl,imx6q", + "fsl,imx6s", NULL, }; -DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") +DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Q/DL/S (Device Tree)") .smp = smp_ops(imx_smp_ops), .map_io = imx6q_map_io, .init_irq = imx6q_init_irq,