From patchwork Fri Sep 6 15:43:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 273238 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C50102C0180 for ; Sat, 7 Sep 2013 01:44:08 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752966Ab3IFPoG (ORCPT ); Fri, 6 Sep 2013 11:44:06 -0400 Received: from mail-db8lp0188.outbound.messaging.microsoft.com ([213.199.154.188]:41108 "EHLO db8outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754063Ab3IFPoF (ORCPT ); Fri, 6 Sep 2013 11:44:05 -0400 Received: from mail122-db8-R.bigfish.com (10.174.8.240) by DB8EHSOBE029.bigfish.com (10.174.4.92) with Microsoft SMTP Server id 14.1.225.22; Fri, 6 Sep 2013 15:44:03 +0000 Received: from mail122-db8 (localhost [127.0.0.1]) by mail122-db8-R.bigfish.com (Postfix) with ESMTP id 33DE722010F; Fri, 6 Sep 2013 15:44:03 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h1de097h8275bh8275dhz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h1155h) Received: from mail122-db8 (localhost.localdomain [127.0.0.1]) by mail122-db8 (MessageSwitch) id 1378482241378620_6868; Fri, 6 Sep 2013 15:44:01 +0000 (UTC) Received: from DB8EHSMHS014.bigfish.com (unknown [10.174.8.252]) by mail122-db8.bigfish.com (Postfix) with ESMTP id 57B864801C5; Fri, 6 Sep 2013 15:44:01 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS014.bigfish.com (10.174.4.24) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 6 Sep 2013 15:44:01 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.3.158.2; Fri, 6 Sep 2013 15:43:59 +0000 Received: from oslab-l1.am.freescale.net ([10.214.81.253]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r86Fha8H011980; Fri, 6 Sep 2013 08:43:58 -0700 From: York Sun To: CC: , York Sun , Subject: [PATCH 4/7] power/mpc85xx: Add delay after enabling I2C master Date: Fri, 6 Sep 2013 08:43:16 -0700 Message-ID: <1378482199-10581-4-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1378482199-10581-1-git-send-email-yorksun@freescale.com> References: <1378482199-10581-1-git-send-email-yorksun@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Erratum A-006037 indicates I2C controller executes the write to I2CCR only after it sees SCL idle for 64K cycle of internal I2C controller clocks. If during this waiting period, I2C controller is disabled (I2CCR[MEN] set to 0), then the controller could end in bad state, and hang the future access to I2C register. The mpc_i2c_fixup() function tries to recover the bus from a stalled state where the 9th clock pulse wasn't generated. However, this workaround disables and enables I2C controller without meeting waiting requirement of this erratum. This erratum applies to some 85xx SoCs. It is safe to apply to all of them for mpc_i2c_fixup(). Signed-off-by: York Sun Reviewed-by: Wood Scott-B07421 Reviewed-by: Fleming Andrew-AFLEMING Tested-by: Fleming Andrew-AFLEMING CC: linux-i2c@vger.kernel.org --- drivers/i2c/busses/i2c-mpc.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c index b80c768..55dce43 100644 --- a/drivers/i2c/busses/i2c-mpc.c +++ b/drivers/i2c/busses/i2c-mpc.c @@ -106,7 +106,12 @@ static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) static void mpc_i2c_fixup(struct mpc_i2c *i2c) { int k; - u32 delay_val = 1000000 / i2c->real_clk + 1; + u32 delay_val; +#ifdef CONFIG_PPC_85xx + delay_val = 65536 / (fsl_get_sys_freq() / 2000000); /* 64K cycle */ +#else + delay_val = 1000000 / i2c->real_clk + 1; +#endif if (delay_val < 2) delay_val = 2; @@ -116,7 +121,11 @@ static void mpc_i2c_fixup(struct mpc_i2c *i2c) writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN); udelay(delay_val); writeccr(i2c, CCR_MEN); +#ifdef CONFIG_PPC_85xx + udelay(delay_val); +#else udelay(delay_val << 1); +#endif } }