Patchwork [AArch64,ARM] Rename the FCPYS type to FMOV

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Submitter James Greenhalgh
Date Sept. 6, 2013, 1:44 p.m.
Message ID <1378475043-16619-1-git-send-email-james.greenhalgh@arm.com>
Download mbox | patch
Permalink /patch/273201/
State New
Headers show

Comments

James Greenhalgh - Sept. 6, 2013, 1:44 p.m.
Hi,

This patch updates the AArch64 backend such that floating point
moves are correctly categorized with type "FMOV".

Then in the ARM backend we rename "FCPYS" to "FMOV" everywhere
where it is appropriate to do so.

Regression tested on aarch64-none-elf and arm-none-eabi with no
regressions.

OK?

Thanks,
James
---
gcc/

2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/types.md (type): Rename fcpys to fmov.
	* config/arm/vfp.md
	(*arm_movsi_vfp): Rename type fcpys as fmov.
	(*thumb2_movsi_vfp): Likewise
	(*movhf_vfp_neon): Likewise
	(*movhf_vfp): Likewise
	(*movsf_vfp): Likewise
	(*thumb2_movsf_vfp): Likewise
	(*movsfcc_vfp): Likewise
	(*thumb2_movsfcc_vfp): Likewise
	* config/aarch64/aarch64-simd.md
	(move_lo_quad_<mode>): Replace type mov_reg with fmovs.
	* config/aarch64/aarch64.md
	(*movsi_aarch64): Replace type mov_reg with fmovs.
	(*movdi_aarch64): Likewise
	(*movsf_aarch64): Likewise
	(*movdf_aarch64): Likewise
	* config/arm/arm.c
	(cortexa7_older_only): Rename TYPE_FCPYS to TYPE_FMOV.
	* config/arm/iwmmxt.md
	(*iwmmxt_movsi_insn): Rename type fcpys as fmov.
	* config/arm/arm1020e.md: Update with new attributes.
	* config/arm/cortex-a15-neon.md: Update with new attributes.
	* config/arm/cortex-a5.md: Update with new attributes.
	* config/arm/cortex-a53.md: Update with new attributes.
	* config/arm/cortex-a7.md: Update with new attributes.
	* config/arm/cortex-a8-neon.md: Update with new attributes.
	* config/arm/cortex-a9.md: Update with new attributes.
	* config/arm/cortex-m4-fpu.md: Update with new attributes.
	* config/arm/cortex-r4f.md: Update with new attributes.
	* config/arm/marvell-pj4.md: Update with new attributes.
	* config/arm/vfp11.md: Update with new attributes.
Richard Earnshaw - Sept. 6, 2013, 1:49 p.m.
On 06/09/13 14:44, James Greenhalgh wrote:
> 
> Hi,
> 
> This patch updates the AArch64 backend such that floating point
> moves are correctly categorized with type "FMOV".
> 
> Then in the ARM backend we rename "FCPYS" to "FMOV" everywhere
> where it is appropriate to do so.
> 
> Regression tested on aarch64-none-elf and arm-none-eabi with no
> regressions.
> 
> OK?
> 
> Thanks,
> James
> ---
> gcc/
> 
> 2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>
> 
> 	* config/arm/types.md (type): Rename fcpys to fmov.
> 	* config/arm/vfp.md
> 	(*arm_movsi_vfp): Rename type fcpys as fmov.
> 	(*thumb2_movsi_vfp): Likewise
> 	(*movhf_vfp_neon): Likewise
> 	(*movhf_vfp): Likewise
> 	(*movsf_vfp): Likewise
> 	(*thumb2_movsf_vfp): Likewise
> 	(*movsfcc_vfp): Likewise
> 	(*thumb2_movsfcc_vfp): Likewise
> 	* config/aarch64/aarch64-simd.md
> 	(move_lo_quad_<mode>): Replace type mov_reg with fmovs.
> 	* config/aarch64/aarch64.md
> 	(*movsi_aarch64): Replace type mov_reg with fmovs.
> 	(*movdi_aarch64): Likewise
> 	(*movsf_aarch64): Likewise
> 	(*movdf_aarch64): Likewise
> 	* config/arm/arm.c
> 	(cortexa7_older_only): Rename TYPE_FCPYS to TYPE_FMOV.
> 	* config/arm/iwmmxt.md
> 	(*iwmmxt_movsi_insn): Rename type fcpys as fmov.
> 	* config/arm/arm1020e.md: Update with new attributes.
> 	* config/arm/cortex-a15-neon.md: Update with new attributes.
> 	* config/arm/cortex-a5.md: Update with new attributes.
> 	* config/arm/cortex-a53.md: Update with new attributes.
> 	* config/arm/cortex-a7.md: Update with new attributes.
> 	* config/arm/cortex-a8-neon.md: Update with new attributes.
> 	* config/arm/cortex-a9.md: Update with new attributes.
> 	* config/arm/cortex-m4-fpu.md: Update with new attributes.
> 	* config/arm/cortex-r4f.md: Update with new attributes.
> 	* config/arm/marvell-pj4.md: Update with new attributes.
> 	* config/arm/vfp11.md: Update with new attributes.
> 
> 

OK.

R.

Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index c085fb9c49958c5f402a28c0b39fe45ec1aadbc7..882fe4a19368d6ef6f9ef862dffce6d6307c5ac3 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1052,7 +1052,7 @@  (define_insn "move_lo_quad_<mode>"
    fmov\\t%d0, %1
    dup\\t%d0, %1"
   [(set_attr "v8type" "*,fmov,*")
-   (set_attr "type" "*,mov_reg,*")
+   (set_attr "type" "*,fmov,*")
    (set_attr "simd_type" "simd_dup,*,simd_dup")
    (set_attr "simd_mode" "<MODE>")
    (set_attr "simd" "yes,*,yes")
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index e28764da5dd608259098d3150783e6eacd09be27..db6aa1d3fa15e17095ba26a64e020d098e9fa6c0 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -831,7 +831,7 @@  (define_insn "*movsi_aarch64"
    fmov\\t%s0, %s1"
   [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov")
    (set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
-                     adr,adr,mov_reg,mov_reg,mov_reg")
+                     adr,adr,fmov,fmov,fmov")
    (set_attr "mode" "SI")
    (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")]
 )
@@ -858,7 +858,7 @@  (define_insn "*movdi_aarch64"
    movi\\t%d0, %1"
   [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov,fmov")
    (set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
-                     adr,adr,mov_reg,mov_reg,mov_reg,mov_reg")
+                     adr,adr,fmov,fmov,fmov,fmov")
    (set_attr "mode" "DI")
    (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
    (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
@@ -961,8 +961,8 @@  (define_insn "*movsf_aarch64"
   [(set_attr "v8type" "fmovi2f,fmovf2i,\
 		       fmov,fconst,fpsimd_load,\
 		       fpsimd_store,fpsimd_load,fpsimd_store,fmov")
-   (set_attr "type" "f_mcr,f_mrc,mov_reg,fconsts,\
-                     f_loads,f_stores,f_loads,f_stores,mov_reg")
+   (set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\
+                     f_loads,f_stores,f_loads,f_stores,fmov")
    (set_attr "mode" "SF")]
 )
 
@@ -984,7 +984,7 @@  (define_insn "*movdf_aarch64"
   [(set_attr "v8type" "fmovi2f,fmovf2i,\
 		       fmov,fconst,fpsimd_load,\
 		       fpsimd_store,fpsimd_load,fpsimd_store,move")
-   (set_attr "type" "f_mcr,f_mrc,mov_reg,fconstd,\
+   (set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\
                      f_loadd,f_stored,f_loadd,f_stored,mov_reg")
    (set_attr "mode" "DF")]
 )
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index cac98cc..f9027dd 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -8977,7 +8977,7 @@  cortexa7_older_only (rtx insn)
     case TYPE_FADDS:
     case TYPE_FFARITHD:
     case TYPE_FADDD:
-    case TYPE_FCPYS:
+    case TYPE_FMOV:
     case TYPE_F_CVT:
     case TYPE_FCMPS:
     case TYPE_FCMPD:
diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md
index 8cf0890d9300527962b14f60e08c190155616425..7df84d5248156b42899812e0172e6e39c7eb41b5 100644
--- a/gcc/config/arm/arm1020e.md
+++ b/gcc/config/arm/arm1020e.md
@@ -279,7 +279,7 @@  (define_attr "vfp10" "yes,no"
 ;; first execute state.  We model this by using 1020a_e in the first cycle.
 (define_insn_reservation "v10_ffarith" 5
  (and (eq_attr "vfp10" "yes")
-      (eq_attr "type" "fcpys,ffariths,ffarithd,fcmps,fcmpd"))
+      (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd"))
  "1020a_e+v10_fmac")
 
 (define_insn_reservation "v10_farith" 5
diff --git a/gcc/config/arm/cortex-a15-neon.md b/gcc/config/arm/cortex-a15-neon.md
index 057507a762ab546e37b4a32a9771b4098a693d55..6eb8268321a6d89d3f8231a26739d6590e15c8d6 100644
--- a/gcc/config/arm/cortex-a15-neon.md
+++ b/gcc/config/arm/cortex-a15-neon.md
@@ -491,7 +491,7 @@  (define_insn_reservation "cortex_a15_vfp
 
 (define_insn_reservation "cortex_a15_vfp_cpys" 4
   (and (eq_attr "tune" "cortexa15")
-       (eq_attr "type" "fcpys"))
+       (eq_attr "type" "fmov"))
   "ca15_issue1,ca15_cx_perm")
 
 (define_insn_reservation "cortex_a15_vfp_ariths" 7
diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md
index 03d3cc99106f4e8875b649b06dbd1341f18a5f55..fa3e9d59c91028214ca7aa1be2c6668b4af5e6d3 100644
--- a/gcc/config/arm/cortex-a5.md
+++ b/gcc/config/arm/cortex-a5.md
@@ -168,7 +168,7 @@  (define_insn_reservation "cortex_a5_bran
 
 (define_insn_reservation "cortex_a5_fpalu" 4
   (and (eq_attr "tune" "cortexa5")
-       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls,\
+       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov, fmuls,\
                         f_cvt,f_cvtf2i,f_cvti2f,\
 			fcmps, fcmpd"))
   "cortex_a5_ex1+cortex_a5_fpadd_pipe")
diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md
index e52f4377c62f217172c2f0b88af724f59ed7cef0..33b5ca30150fc57e7a3c4886c01b9e8092fc3ffa 100644
--- a/gcc/config/arm/cortex-a53.md
+++ b/gcc/config/arm/cortex-a53.md
@@ -209,7 +209,7 @@  (define_insn_reservation "cortex_a53_bra
 
 (define_insn_reservation "cortex_a53_fpalu" 4
   (and (eq_attr "tune" "cortexa53")
-       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls,\
+       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov, fmuls,\
                         f_cvt,f_cvtf2i,f_cvti2f,\
 			fcmps, fcmpd, fcsel"))
   "cortex_a53_slot0+cortex_a53_fpadd_pipe")
diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md
index 97b4cadb7c89e470d0c49c3f6b2b8e19008137e7..ba9da8046ebd4a886c425238ab28df5ab9d85a8a 100644
--- a/gcc/config/arm/cortex-a7.md
+++ b/gcc/config/arm/cortex-a7.md
@@ -204,7 +204,7 @@  (define_insn_reservation "cortex_a7_stor
 
 (define_insn_reservation "cortex_a7_fpalu" 4
   (and (eq_attr "tune" "cortexa7")
-       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\
+       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov,\
                         f_cvt, f_cvtf2i, f_cvti2f, fcmps, fcmpd"))
   "cortex_a7_ex1+cortex_a7_fpadd_pipe")
 
diff --git a/gcc/config/arm/cortex-a8-neon.md b/gcc/config/arm/cortex-a8-neon.md
index ad3dd773bf86ce4d1e73bc842b7d303b7b4e3548..b7773891669061d3f08b4a74de9881db982aa246 100644
--- a/gcc/config/arm/cortex-a8-neon.md
+++ b/gcc/config/arm/cortex-a8-neon.md
@@ -172,7 +172,7 @@  (define_insn_reservation "cortex_a8_vfp_
 ;; take four cycles, we pick that latency.
 (define_insn_reservation "cortex_a8_vfp_farith" 4
   (and (eq_attr "tune" "cortexa8")
-       (eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,fcmps,fcmpd"))
+       (eq_attr "type" "fmov,ffariths,ffarithd,fconsts,fconstd,fcmps,fcmpd"))
   "cortex_a8_vfp,cortex_a8_vfplite*3")
 
 (define_insn_reservation "cortex_a8_vfp_cvt" 7
diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md
index 32514686bb0a5857aeb10021d54614a9e76a0fbb..dd7505a0cf54cd288c5e7cea675017bab4be9ba4 100644
--- a/gcc/config/arm/cortex-a9.md
+++ b/gcc/config/arm/cortex-a9.md
@@ -207,7 +207,7 @@  (define_insn_reservation "cortex_a9_call
 ;; Pipelining for VFP instructions.
 ;; Issue happens either along load store unit or the VFP / Neon unit.
 ;; Pipeline   Instruction Classification.
-;; FPS - fcpys, ffariths, ffarithd,f_mcr,f_mcrr,f_mrc,f_mrrc
+;; FPS - fmov, ffariths, ffarithd,f_mcr,f_mcrr,f_mrc,f_mrrc
 ;; FP_ADD   - fadds, faddd, fcmps (1)
 ;; FPMUL   - fmul{s,d}, fmac{s,d}, ffma{s,d}
 ;; FPDIV - fdiv{s,d}
@@ -220,7 +220,7 @@  (define_cpu_unit "ca9fp_ds1" "cortex_a9"
 ;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle.
 (define_insn_reservation "cortex_a9_fps" 2
  (and (eq_attr "tune" "cortexa9")
-      (eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd,\
+      (eq_attr "type" "fmov, fconsts, fconstd, ffariths, ffarithd,\
                        f_mcr, f_mcrr, f_mrc, f_mrrc, f_flag"))
  "ca9_issue_vfp_neon + ca9fps")
 
diff --git a/gcc/config/arm/cortex-m4-fpu.md b/gcc/config/arm/cortex-m4-fpu.md
index e130cf7d5fcc3088a88406daec8901209df08fef..2190938b65c2dae9db222371142c0141b1533078 100644
--- a/gcc/config/arm/cortex-m4-fpu.md
+++ b/gcc/config/arm/cortex-m4-fpu.md
@@ -35,7 +35,7 @@  (define_insn_reservation "cortex_m4_fdiv
 
 (define_insn_reservation "cortex_m4_vmov_1" 1
   (and (eq_attr "tune" "cortexm4")
-       (eq_attr "type" "fcpys,fconsts"))
+       (eq_attr "type" "fmov,fconsts"))
   "cortex_m4_ex_v")
 
 (define_insn_reservation "cortex_m4_vmov_2" 2
diff --git a/gcc/config/arm/cortex-r4f.md b/gcc/config/arm/cortex-r4f.md
index 8f357da106157563388fee7079102ca94565cbd9..1bc4249d4d1fdf5afa75ae5168dd9290904750e6 100644
--- a/gcc/config/arm/cortex-r4f.md
+++ b/gcc/config/arm/cortex-r4f.md
@@ -48,7 +48,7 @@  (define_reservation "cortex_r4_single_is
 
 (define_insn_reservation "cortex_r4_fcpys" 2
  (and (eq_attr "tune_cortexr4" "yes")
-      (eq_attr "type" "fcpys"))
+      (eq_attr "type" "fmov"))
  "cortex_r4_issue_ab")
 
 (define_insn_reservation "cortex_r4_ffariths" 2
diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md
index 3966715d4732b1e20fe6ddfbc4071e415292c410..62cdae21e3f33b47c95123d2c7ca64dda64d7a5c 100644
--- a/gcc/config/arm/iwmmxt.md
+++ b/gcc/config/arm/iwmmxt.md
@@ -189,7 +189,7 @@  (define_insn "*iwmmxt_movsi_insn"
        gcc_unreachable ();
      }"
   [(set_attr "type"           "*,*,*,*,load1,store1,*,*,*,*,f_mcr,f_mrc,\
-                               fcpys,f_loads,f_stores")
+                               fmov,f_loads,f_stores")
    (set_attr "length"         "*,*,*,*,*,        *,*,*,  16,     *,*,*,*,*,*")
    (set_attr "pool_range"     "*,*,*,*,4096,     *,*,*,1024,     *,*,*,*,1020,*")
    (set_attr "neg_pool_range" "*,*,*,*,4084,     *,*,*,   *,  1012,*,*,*,1008,*")
diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md
index a2a9785b5f2797d6482f3f44fee2520ff976983e..880789600e0dedbd1ce05e2a1f6ef23ebcb43f13 100644
--- a/gcc/config/arm/marvell-pj4.md
+++ b/gcc/config/arm/marvell-pj4.md
@@ -208,7 +208,7 @@  (define_bypass 5 "pj4_vfp_mac" "pj4_vfp_
 
 (define_insn_reservation "pj4_vfp_cpy"  4
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,\
+       (eq_attr "type" "fmov,ffariths,ffarithd,fconsts,fconstd,\
                         fcmps,fcmpd,f_cvt,f_cvtf2i,f_cvti2f"))
 "pj4_is,nothing*2,vissue,vfast,nothing*2")
 
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index bf5fae79d988360a29c89b06c068c7011ac98e37..6c2db277dca7ff9e34db0e945f5114aaa0994202 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -71,13 +71,13 @@ 
 ; fadd[d,s]          double/single floating-point scalar addition.
 ; fcmp[d,s]          double/single floating-point compare.
 ; fconst[d,s]        double/single load immediate.
-; fcpys              single precision floating point cpy.
 ; fcsel              From ARMv8-A: Floating-point conditional select.
 ; fdiv[d,s]          double/single precision floating point division.
 ; ffarith[d,s]       double/single floating point abs/neg/cpy.
 ; ffma[d,s]          double/single floating point fused multiply-accumulate.
 ; float              floating point arithmetic operation.
 ; fmac[d,s]          double/single floating point multiply-accumulate.
+; fmov               floating point to floating point register move.
 ; fmul[d,s]          double/single floating point multiply.
 ; fsqrt[d,s]         double/single precision floating point square root.
 ; load_acq           load-acquire.
@@ -337,7 +337,6 @@  (define_attr "type"
   fcmps,\
   fconstd,\
   fconsts,\
-  fcpys,\
   fcsel,\
   fdivd,\
   fdivs,\
@@ -348,6 +347,7 @@  (define_attr "type"
   float,\
   fmacd,\
   fmacs,\
+  fmov,\
   fmuld,\
   fmuls,\
   fsqrts,\
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 3001751e74970f689aa19334319a59d97a7a4b2d..9318e49d9ea6fcbd4783c749aa6db43ac7fa8265 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -53,7 +53,7 @@  (define_insn "*arm_movsi_vfp"
     }
   "
   [(set_attr "predicable" "yes")
-   (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fcpys,f_loads,f_stores")
+   (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
    (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
 )
@@ -100,7 +100,7 @@  (define_insn "*thumb2_movsi_vfp"
   "
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no")
-   (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,f_mcr,f_mrc,fcpys,f_loads,f_stores")
+   (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
    (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4")
    (set_attr "pool_range"     "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*")
    (set_attr "neg_pool_range" "*,*,*,*,*,   0,   0,*,*,*,*,*,1008,*")]
@@ -261,7 +261,7 @@  (define_insn "*movhf_vfp_neon"
   "
   [(set_attr "conds" "unconditional")
    (set_attr "type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,\
-                     load1,store1,fcpys,mov_reg,f_mcr,f_mrc,multiple")
+                     load1,store1,fmov,mov_reg,f_mcr,f_mrc,multiple")
    (set_attr "length" "4,4,4,4,4,4,4,4,8")]
 )
 
@@ -311,7 +311,7 @@  (define_insn "*movhf_vfp"
     }
   "
   [(set_attr "conds" "unconditional")
-   (set_attr "type" "load1,store1,fcpys,mov_reg,f_mcr,f_mrc,multiple")
+   (set_attr "type" "load1,store1,fmov,mov_reg,f_mcr,f_mrc,multiple")
    (set_attr "length" "4,4,4,4,4,4,8")]
 )
 
@@ -351,7 +351,7 @@  (define_insn "*movsf_vfp"
   "
   [(set_attr "predicable" "yes")
    (set_attr "type"
-     "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg")
+     "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg")
    (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
    (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
 )
@@ -388,7 +388,7 @@  (define_insn "*thumb2_movsf_vfp"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
    (set_attr "type"
-     "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg")
+     "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg")
    (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
    (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
 )
@@ -509,7 +509,7 @@  (define_insn "*movsfcc_vfp"
    fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
    [(set_attr "conds" "use")
     (set_attr "length" "4,4,8,4,4,8,4,4,8")
-    (set_attr "type" "fcpys,fcpys,fcpys,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
+    (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
 )
 
 (define_insn "*thumb2_movsfcc_vfp"
@@ -532,7 +532,7 @@  (define_insn "*thumb2_movsfcc_vfp"
    ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
    [(set_attr "conds" "use")
     (set_attr "length" "6,6,10,6,6,10,6,6,10")
-    (set_attr "type" "fcpys,fcpys,fcpys,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
+    (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
 )
 
 (define_insn "*movdfcc_vfp"
diff --git a/gcc/config/arm/vfp11.md b/gcc/config/arm/vfp11.md
index 8b76ce198f02bcf9e46af4925f0f3d928f3b6992..4cfa69efc24581434917a97988c4e3569ece40d8 100644
--- a/gcc/config/arm/vfp11.md
+++ b/gcc/config/arm/vfp11.md
@@ -51,7 +51,7 @@  (define_cpu_unit "fmstat" "vfp11")
 
 (define_insn_reservation "vfp_ffarith" 4
  (and (eq_attr "generic_vfp" "yes")
-      (eq_attr "type" "fcpys,ffariths,ffarithd,fcmps,fcmpd"))
+      (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd"))
  "fmac")
 
 (define_insn_reservation "vfp_farith" 8