From patchwork Fri Sep 6 13:27:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Greenhalgh X-Patchwork-Id: 273196 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "www.sourceware.org", Issuer "StartCom Class 1 Primary Intermediate Server CA" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 27AB92C007A for ; Fri, 6 Sep 2013 23:27:45 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=FJoqZVdPWKo0Yg69JRnYA8OI7DD6Nq7ogFBgIePq4CpO4r5I6u 9aeNpS/Iv1GiosicqpjKQn4Him2VB0QdbzD15u5eji5qceAES+h322rZxh3ZXjYP YnTuXeFi0kjrmHaJ307mYTqjJ5m3k2Os5j2Mx3SvPa+Yn8WPT2L3lCfdA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=jfhE+KdZxMU2Ox1wnvhh8/FeHdM=; b=Vd0Ku7pZVfn/SiTPKd0C 3DRPWBthvOHBD0GgkFIhb03/lreWcuNlJ9Gk69mFVGoM/XE6wlEtGruKSpmEaeqL 1cS5nOIb5fKTt/gJa7zmAoPETJKMwN1yqaOQM0ET9rKD1GCg8dGzkR1zxLnmDQsM wR+ysqvdM1I2uAQxeLs/QSg= Received: (qmail 32077 invoked by alias); 6 Sep 2013 13:27:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 32066 invoked by uid 89); 6 Sep 2013 13:27:39 -0000 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 06 Sep 2013 13:27:39 +0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_NO, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 06 Sep 2013 14:27:34 +0100 Received: from e106375-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Fri, 6 Sep 2013 14:27:33 +0100 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: marcus.shawcroft@arm.com, ramana.radhakrishnan@arm.com, richard.earnshaw@arm.com Subject: [Patch ARM AARCH64] Split "type" attributes: fdiv Date: Fri, 6 Sep 2013 14:27:24 +0100 Message-Id: <1378474044-6005-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: 113090614273402001 X-IsSubscribed: yes Hi, The type attributes "fdivs,fdivd" should be split as: fdivs -> fsqrts, fdivs fdivd -> fsqrtd, fdivd Do this and update pipelines as needed. Regression tested on aarch64-none-elf and arm-none-eabi and bootstrapped in series with other type splitting patches. OK? Thanks, James --- 2013-09-06 James Greenhalgh * config/arm/types.md: Split fdiv as fsqrt, fdiv. * config/arm/arm.md (core_cycles): Remove fdiv. * config/arm/vfp.md: (*sqrtsf2_vfp): Update for attribute changes. (*sqrtdf2_vfp): Likewise. * config/aarch64/aarch64.md: (sqrt2): Update for attribute changes. * config/arm/arm1020e.md: Update with new attributes. * config/arm/cortex-a15-neon.md: Update with new attributes. * config/arm/cortex-a5.md: Update with new attributes. * config/arm/cortex-a53.md: Update with new attributes. * config/arm/cortex-a7.md: Update with new attributes. * config/arm/cortex-a8-neon.md: Update with new attributes. * config/arm/cortex-a9.md: Update with new attributes. * config/arm/cortex-m4-fpu.md: Update with new attributes. * config/arm/cortex-r4f.md: Update with new attributes. * config/arm/marvell-pj4.md: Update with new attributes. * config/arm/vfp11.md: Update with new attributes. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 6a4a975bb89c48311659db0091c76266d29cdba2..ded37efb4c86130af8dd82db66d50cc227bfeff0 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3903,7 +3903,7 @@ (define_insn "sqrt2" "TARGET_FLOAT" "fsqrt\\t%0, %1" [(set_attr "v8type" "fsqrt") - (set_attr "type" "fdiv") + (set_attr "type" "fsqrt") (set_attr "mode" "")] ) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 5ed8ee7dc6293bf93869545bef4cd3f60966908b..6c0fbf44288c9f6e077fe2d9836cd5c1e2042a0a 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -335,7 +335,6 @@ (define_attr "core_cycles" "single,multi alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\ logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\ logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\ - fdivd, fdivs,\ wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\ wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\ wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\ diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md index e16e862c1f49b36f75ba1faf20c2095fb9aeacdf..8cf0890d9300527962b14f60e08c190155616425 100644 --- a/gcc/config/arm/arm1020e.md +++ b/gcc/config/arm/arm1020e.md @@ -299,12 +299,12 @@ (define_insn_reservation "v10_fmul" 6 (define_insn_reservation "v10_fdivs" 18 (and (eq_attr "vfp10" "yes") - (eq_attr "type" "fdivs")) + (eq_attr "type" "fdivs, fsqrts")) "1020a_e+v10_ds*14") (define_insn_reservation "v10_fdivd" 32 (and (eq_attr "vfp10" "yes") - (eq_attr "type" "fdivd")) + (eq_attr "type" "fdivd, fsqrtd")) "1020a_e+v10_fmac+v10_ds*28") (define_insn_reservation "v10_floads" 4 diff --git a/gcc/config/arm/cortex-a15-neon.md b/gcc/config/arm/cortex-a15-neon.md index b5d14e7f7f9c3965e02e0d6e0edf0044df341812..057507a762ab546e37b4a32a9771b4098a693d55 100644 --- a/gcc/config/arm/cortex-a15-neon.md +++ b/gcc/config/arm/cortex-a15-neon.md @@ -501,12 +501,12 @@ (define_insn_reservation "cortex_a15_vfp (define_insn_reservation "cortex_a15_vfp_divs" 10 (and (eq_attr "tune" "cortexa15") - (eq_attr "type" "fdivs")) + (eq_attr "type" "fdivs, fsqrts")) "ca15_issue1,ca15_cx_ik") (define_insn_reservation "cortex_a15_vfp_divd" 18 (and (eq_attr "tune" "cortexa15") - (eq_attr "type" "fdivd")) + (eq_attr "type" "fdivd, fsqrtd")) "ca15_issue1,ca15_cx_ik") ;; Define bypasses. diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md index 54c8c420324a155523bc961917c475c5aeb86a96..03d3cc99106f4e8875b649b06dbd1341f18a5f55 100644 --- a/gcc/config/arm/cortex-a5.md +++ b/gcc/config/arm/cortex-a5.md @@ -233,14 +233,14 @@ (define_insn_reservation "cortex_a5_fpma (define_insn_reservation "cortex_a5_fdivs" 14 (and (eq_attr "tune" "cortexa5") - (eq_attr "type" "fdivs")) + (eq_attr "type" "fdivs, fsqrts")) "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13") ;; ??? Similarly for fdivd. (define_insn_reservation "cortex_a5_fdivd" 29 (and (eq_attr "tune" "cortexa5") - (eq_attr "type" "fdivd")) + (eq_attr "type" "fdivd, fsqrtd")) "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index e84b9ea1a71ef1df2476d3b25900522469074914..e52f4377c62f217172c2f0b88af724f59ed7cef0 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -239,12 +239,12 @@ (define_insn_reservation "cortex_a53_fpm (define_insn_reservation "cortex_a53_fdivs" 14 (and (eq_attr "tune" "cortexa53") - (eq_attr "type" "fdivs")) + (eq_attr "type" "fdivs, fsqrts")) "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 13") (define_insn_reservation "cortex_a53_fdivd" 29 (and (eq_attr "tune" "cortexa53") - (eq_attr "type" "fdivd")) + (eq_attr "type" "fdivd, fsqrtd")) "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 28") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md index 6d7b43685a3afe8f89e7b1d9f336326f511fea7b..97b4cadb7c89e470d0c49c3f6b2b8e19008137e7 100644 --- a/gcc/config/arm/cortex-a7.md +++ b/gcc/config/arm/cortex-a7.md @@ -288,12 +288,12 @@ (define_bypass 7 "cortex_a7_fpmacd" (define_insn_reservation "cortex_a7_fdivs" 16 (and (eq_attr "tune" "cortexa7") - (eq_attr "type" "fdivs")) + (eq_attr "type" "fdivs, fsqrts")) "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 13") (define_insn_reservation "cortex_a7_fdivd" 31 (and (eq_attr "tune" "cortexa7") - (eq_attr "type" "fdivd")) + (eq_attr "type" "fdivd, fsqrtd")) "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 28") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/cortex-a8-neon.md b/gcc/config/arm/cortex-a8-neon.md index 6953a9590a5c486bf4817ff2521caa299c8ecf93..ad3dd773bf86ce4d1e73bc842b7d303b7b4e3548 100644 --- a/gcc/config/arm/cortex-a8-neon.md +++ b/gcc/config/arm/cortex-a8-neon.md @@ -159,12 +159,12 @@ (define_insn_reservation "cortex_a8_vfp_ (define_insn_reservation "cortex_a8_vfp_divs" 37 (and (eq_attr "tune" "cortexa8") - (eq_attr "type" "fdivs")) + (eq_attr "type" "fdivs, fsqrts")) "cortex_a8_vfp,cortex_a8_vfplite*36") (define_insn_reservation "cortex_a8_vfp_divd" 65 (and (eq_attr "tune" "cortexa8") - (eq_attr "type" "fdivd")) + (eq_attr "type" "fdivd, fsqrtd")) "cortex_a8_vfp,cortex_a8_vfplite*64") ;; Comparisons can actually take 7 cycles sometimes instead of four, diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md index a66481807cf4c9263d0b565b370d6057d21a043e..32514686bb0a5857aeb10021d54614a9e76a0fbb 100644 --- a/gcc/config/arm/cortex-a9.md +++ b/gcc/config/arm/cortex-a9.md @@ -271,12 +271,12 @@ (define_insn_reservation "cortex_a9_fmac ;; Division pipeline description. (define_insn_reservation "cortex_a9_fdivs" 15 (and (eq_attr "tune" "cortexa9") - (eq_attr "type" "fdivs")) + (eq_attr "type" "fdivs, fsqrts")) "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*14") (define_insn_reservation "cortex_a9_fdivd" 25 (and (eq_attr "tune" "cortexa9") - (eq_attr "type" "fdivd")) + (eq_attr "type" "fdivd, fsqrtd")) "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24") ;; Include Neon pipeline description diff --git a/gcc/config/arm/cortex-m4-fpu.md b/gcc/config/arm/cortex-m4-fpu.md index 81c12b74f65cf6fe113b77cb4368af5383916c44..e130cf7d5fcc3088a88406daec8901209df08fef 100644 --- a/gcc/config/arm/cortex-m4-fpu.md +++ b/gcc/config/arm/cortex-m4-fpu.md @@ -30,7 +30,7 @@ (define_reservation "cortex_m4_exb_vb" " ;; Integer instructions following VDIV or VSQRT complete out-of-order. (define_insn_reservation "cortex_m4_fdivs" 15 (and (eq_attr "tune" "cortexm4") - (eq_attr "type" "fdivs")) + (eq_attr "type" "fdivs, fsqrts")) "cortex_m4_ex_v,cortex_m4_v*13") (define_insn_reservation "cortex_m4_vmov_1" 1 diff --git a/gcc/config/arm/cortex-r4f.md b/gcc/config/arm/cortex-r4f.md index 06e061e2b1451afcd7207186a2875cc2da3c771c..8f357da106157563388fee7079102ca94565cbd9 100644 --- a/gcc/config/arm/cortex-r4f.md +++ b/gcc/config/arm/cortex-r4f.md @@ -68,7 +68,7 @@ (define_insn_reservation "cortex_r4_fmac (define_insn_reservation "cortex_r4_fdivs" 17 (and (eq_attr "tune_cortexr4" "yes") - (eq_attr "type" "fdivs")) + (eq_attr "type" "fdivs, fsqrts")) "cortex_r4_issue_ab+cortex_r4_v1,cortex_r4_issue_a+cortex_r4_v1") (define_insn_reservation "cortex_r4_floads" 2 @@ -131,7 +131,7 @@ (define_insn_reservation "cortex_r4_fari ;; out of order. Chances are this is not a pipelined operation. (define_insn_reservation "cortex_r4_fdivd" 97 (and (eq_attr "tune_cortexr4" "yes") - (eq_attr "type" "fdivd")) + (eq_attr "type" "fdivd, fsqrtd")) "cortex_r4_single_issue*3") (define_insn_reservation "cortex_r4_ffarithd" 2 diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md index d9cf8d4b6b57967be185bcb5f9be0b4f6e2faf9a..a2a9785b5f2797d6482f3f44fee2520ff976983e 100644 --- a/gcc/config/arm/marvell-pj4.md +++ b/gcc/config/arm/marvell-pj4.md @@ -193,11 +193,11 @@ (define_insn_reservation "pj4_vfp_mul" (define_insn_reservation "pj4_vfp_divs" 20 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "fdivs")) "pj4_is,nothing*2,vissue,vdiv*18,nothing") + (eq_attr "type" "fdivs, fsqrts")) "pj4_is,nothing*2,vissue,vdiv*18,nothing") (define_insn_reservation "pj4_vfp_divd" 34 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "fdivd")) "pj4_is,nothing*2,vissue,vdiv*32,nothing") + (eq_attr "type" "fdivd, fsqrtd")) "pj4_is,nothing*2,vissue,vdiv*32,nothing") (define_insn_reservation "pj4_vfp_mac" 9 (and (eq_attr "tune" "marvell_pj4") diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index de817634ec98c4c568ade6d1e3d5a8910d886075..bf5fae79d988360a29c89b06c068c7011ac98e37 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -79,6 +79,7 @@ ; float floating point arithmetic operation. ; fmac[d,s] double/single floating point multiply-accumulate. ; fmul[d,s] double/single floating point multiply. +; fsqrt[d,s] double/single precision floating point square root. ; load_acq load-acquire. ; load_byte load byte(s) from memory to arm registers. ; load1 load 1 word from memory to arm registers. @@ -349,6 +350,8 @@ (define_attr "type" fmacs,\ fmuld,\ fmuls,\ + fsqrts,\ + fsqrtd,\ load_acq,\ load_byte,\ load1,\ diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 0e61c6eff004cf764d4fd801a508049f18a1e09f..3001751e74970f689aa19334319a59d97a7a4b2d 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -1077,7 +1077,7 @@ (define_insn "*sqrtsf2_vfp" "fsqrts%?\\t%0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "fdivs")] + (set_attr "type" "fsqrts")] ) (define_insn "*sqrtdf2_vfp" @@ -1087,7 +1087,7 @@ (define_insn "*sqrtdf2_vfp" "fsqrtd%?\\t%P0, %P1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "fdivd")] + (set_attr "type" "fsqrtd")] ) diff --git a/gcc/config/arm/vfp11.md b/gcc/config/arm/vfp11.md index 3cc343e0186d3d64b4f43360a5d94c0429706efa..8b76ce198f02bcf9e46af4925f0f3d928f3b6992 100644 --- a/gcc/config/arm/vfp11.md +++ b/gcc/config/arm/vfp11.md @@ -67,12 +67,12 @@ (define_insn_reservation "vfp_fmul" 9 (define_insn_reservation "vfp_fdivs" 19 (and (eq_attr "generic_vfp" "yes") - (eq_attr "type" "fdivs")) + (eq_attr "type" "fdivs, fsqrts")) "ds*15") (define_insn_reservation "vfp_fdivd" 33 (and (eq_attr "generic_vfp" "yes") - (eq_attr "type" "fdivd")) + (eq_attr "type" "fdivd, fsqrtd")) "fmac+ds*29") ;; Moves to/from arm regs also use the load/store pipeline.