Patchwork [ARM,AARCH64] Insn type reclassification. Split f_cvt type.

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Submitter James Greenhalgh
Date Sept. 6, 2013, 1:24 p.m.
Message ID <1378473885-25560-1-git-send-email-james.greenhalgh@arm.com>
Download mbox | patch
Permalink /patch/273195/
State New
Headers show

Comments

James Greenhalgh - Sept. 6, 2013, 1:24 p.m.
This patch splits the f_cvt attribute to:

 * f_cvt conversions between float representations.
 * f_cvti2f conversions from int to float.
 * f_cvtf2i conversions from float to int.

Then we update the pipeline descriptions to refelct this change.

Regression tested for aarch64-none-elf and arm-none-eabi and sanity
checked. Bootstrapped in series with other type splitting patches.

OK?

Thanks,
James

---
2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/types.md
	(type): Split f_cvt as f_cvt, f_cvtf2i, f_cvti2f.
	* config/aarch64/aarch64.md
	(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): Update with
	new attributes.
	(fix_trunc<GPF:mode><GPI:mode>2): Likewise.
	(fixuns_trunc<GPF:mode><GPI:mode>2): Likewise.
	(float<GPI:mode><GPF:mode>2): Likewise.
	* config/arm/vfp.md
	(*truncsisf2_vfp): Update with new attributes.
	(*truncsidf2_vfp): Likewise.
	(fixuns_truncsfsi2): Likewise.
	(fixuns_truncdfsi2): Likewise.
	(*floatsisf2_vfp): Likewise.
	(*floatsidf2_vfp): Likewise.
	(floatunssisf2): Likewise.
	(floatunssidf2): Likewise.
	(*combine_vcvt_f32_<FCVTI32typename>): Likewise.
	(*combine_vcvt_f64_<FCVTI32typename>): Likewise.
	* config/arm/arm1020e.md: Update with new attributes.
	* config/arm/cortex-a15-neon.md: Update with new attributes.
	* config/arm/cortex-a5.md: Update with new attributes.
	* config/arm/cortex-a53.md: Update with new attributes.
	* config/arm/cortex-a7.md: Update with new attributes.
	* config/arm/cortex-a8-neon.md: Update with new attributes.
	* config/arm/cortex-a9.md: Update with new attributes.
	* config/arm/cortex-m4-fpu.md: Update with new attributes.
	* config/arm/cortex-r4f.md: Update with new attributes.
	* config/arm/marvell-pj4.md: Update with new attributes.
	* config/arm/vfp11.md: Update with new attributes.
Richard Earnshaw - Sept. 6, 2013, 1:33 p.m.
On 06/09/13 14:24, James Greenhalgh wrote:
> 
> This patch splits the f_cvt attribute to:
> 
>  * f_cvt conversions between float representations.
>  * f_cvti2f conversions from int to float.
>  * f_cvtf2i conversions from float to int.
> 
> Then we update the pipeline descriptions to refelct this change.
> 
> Regression tested for aarch64-none-elf and arm-none-eabi and sanity
> checked. Bootstrapped in series with other type splitting patches.
> 
> OK?
> 
> Thanks,
> James
> 
> ---
> 2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>
> 
> 	* config/arm/types.md
> 	(type): Split f_cvt as f_cvt, f_cvtf2i, f_cvti2f.
> 	* config/aarch64/aarch64.md
> 	(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): Update with
> 	new attributes.
> 	(fix_trunc<GPF:mode><GPI:mode>2): Likewise.
> 	(fixuns_trunc<GPF:mode><GPI:mode>2): Likewise.
> 	(float<GPI:mode><GPF:mode>2): Likewise.
> 	* config/arm/vfp.md
> 	(*truncsisf2_vfp): Update with new attributes.
> 	(*truncsidf2_vfp): Likewise.
> 	(fixuns_truncsfsi2): Likewise.
> 	(fixuns_truncdfsi2): Likewise.
> 	(*floatsisf2_vfp): Likewise.
> 	(*floatsidf2_vfp): Likewise.
> 	(floatunssisf2): Likewise.
> 	(floatunssidf2): Likewise.
> 	(*combine_vcvt_f32_<FCVTI32typename>): Likewise.
> 	(*combine_vcvt_f64_<FCVTI32typename>): Likewise.
> 	* config/arm/arm1020e.md: Update with new attributes.
> 	* config/arm/cortex-a15-neon.md: Update with new attributes.
> 	* config/arm/cortex-a5.md: Update with new attributes.
> 	* config/arm/cortex-a53.md: Update with new attributes.
> 	* config/arm/cortex-a7.md: Update with new attributes.
> 	* config/arm/cortex-a8-neon.md: Update with new attributes.
> 	* config/arm/cortex-a9.md: Update with new attributes.
> 	* config/arm/cortex-m4-fpu.md: Update with new attributes.
> 	* config/arm/cortex-r4f.md: Update with new attributes.
> 	* config/arm/marvell-pj4.md: Update with new attributes.
> 	* config/arm/vfp11.md: Update with new attributes.
> 
> 

OK.

R.

Patch

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 4dfd2ab83d00601dc8192ad47fec2c1e404d1264..6a4a975bb89c48311659db0091c76266d29cdba2 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3685,7 +3685,7 @@  (define_insn "l<fcvt_pattern><su_optab><
   "TARGET_FLOAT"
   "fcvt<frint_suffix><su>\\t%<GPI:w>0, %<GPF:s>1"
   [(set_attr "v8type" "fcvtf2i")
-   (set_attr "type" "f_cvt")
+   (set_attr "type" "f_cvtf2i")
    (set_attr "mode" "<GPF:MODE>")
    (set_attr "mode2" "<GPI:MODE>")]
 )
@@ -3785,7 +3785,7 @@  (define_insn "fix_trunc<GPF:mode><GPI:mo
   "TARGET_FLOAT"
   "fcvtzs\\t%<GPI:w>0, %<GPF:s>1"
   [(set_attr "v8type" "fcvtf2i")
-   (set_attr "type" "f_cvt")
+   (set_attr "type" "f_cvtf2i")
    (set_attr "mode" "<GPF:MODE>")
    (set_attr "mode2" "<GPI:MODE>")]
 )
@@ -3796,7 +3796,7 @@  (define_insn "fixuns_trunc<GPF:mode><GPI
   "TARGET_FLOAT"
   "fcvtzu\\t%<GPI:w>0, %<GPF:s>1"
   [(set_attr "v8type" "fcvtf2i")
-   (set_attr "type" "f_cvt")
+   (set_attr "type" "f_cvtf2i")
    (set_attr "mode" "<GPF:MODE>")
    (set_attr "mode2" "<GPI:MODE>")]
 )
@@ -3807,7 +3807,7 @@  (define_insn "float<GPI:mode><GPF:mode>2
   "TARGET_FLOAT"
   "scvtf\\t%<GPF:s>0, %<GPI:w>1"
   [(set_attr "v8type" "fcvti2f")
-   (set_attr "type" "f_cvt")
+   (set_attr "type" "f_cvti2f")
    (set_attr "mode" "<GPF:MODE>")
    (set_attr "mode2" "<GPI:MODE>")]
 )
diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md
index 615c6a5b16de647cbd8c0fa947f8b763a1353ee3..e16e862c1f49b36f75ba1faf20c2095fb9aeacdf 100644
--- a/gcc/config/arm/arm1020e.md
+++ b/gcc/config/arm/arm1020e.md
@@ -289,7 +289,7 @@  (define_insn_reservation "v10_farith" 5
 
 (define_insn_reservation "v10_cvt" 5
  (and (eq_attr "vfp10" "yes")
-      (eq_attr "type" "f_cvt"))
+      (eq_attr "type" "f_cvt,f_cvti2f,f_cvtf2i"))
  "1020a_e+v10_fmac")
 
 (define_insn_reservation "v10_fmul" 6
diff --git a/gcc/config/arm/cortex-a15-neon.md b/gcc/config/arm/cortex-a15-neon.md
index f1cac9e1af88bd5e3f0d87ff50c44376ad82d441..b5d14e7f7f9c3965e02e0d6e0edf0044df341812 100644
--- a/gcc/config/arm/cortex-a15-neon.md
+++ b/gcc/config/arm/cortex-a15-neon.md
@@ -471,7 +471,7 @@  (define_insn_reservation "cortex_a15_vfp
 
 (define_insn_reservation "cortex_a15_vfp_cvt" 6
   (and (eq_attr "tune" "cortexa15")
-       (eq_attr "type" "f_cvt"))
+       (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
   "ca15_issue1,ca15_cx_vfp")
 
 (define_insn_reservation "cortex_a15_vfp_cmpd" 8
diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md
index 8930baf8daff5be2d2872324cd41fd5a1cd03778..54c8c420324a155523bc961917c475c5aeb86a96 100644
--- a/gcc/config/arm/cortex-a5.md
+++ b/gcc/config/arm/cortex-a5.md
@@ -168,7 +168,8 @@  (define_insn_reservation "cortex_a5_bran
 
 (define_insn_reservation "cortex_a5_fpalu" 4
   (and (eq_attr "tune" "cortexa5")
-       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
+       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls,\
+                        f_cvt,f_cvtf2i,f_cvti2f,\
 			fcmps, fcmpd"))
   "cortex_a5_ex1+cortex_a5_fpadd_pipe")
 
diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md
index 66d4cb436f5fb43b545f94ac57a8c5e909360353..e84b9ea1a71ef1df2476d3b25900522469074914 100644
--- a/gcc/config/arm/cortex-a53.md
+++ b/gcc/config/arm/cortex-a53.md
@@ -209,7 +209,8 @@  (define_insn_reservation "cortex_a53_bra
 
 (define_insn_reservation "cortex_a53_fpalu" 4
   (and (eq_attr "tune" "cortexa53")
-       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
+       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls,\
+                        f_cvt,f_cvtf2i,f_cvti2f,\
 			fcmps, fcmpd, fcsel"))
   "cortex_a53_slot0+cortex_a53_fpadd_pipe")
 
diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md
index bd7aecda021ef50209cd6d94758626fa015a123f..6d7b43685a3afe8f89e7b1d9f336326f511fea7b 100644
--- a/gcc/config/arm/cortex-a7.md
+++ b/gcc/config/arm/cortex-a7.md
@@ -205,7 +205,7 @@  (define_insn_reservation "cortex_a7_stor
 (define_insn_reservation "cortex_a7_fpalu" 4
   (and (eq_attr "tune" "cortexa7")
        (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\
-                        f_cvt, fcmps, fcmpd"))
+                        f_cvt, f_cvtf2i, f_cvti2f, fcmps, fcmpd"))
   "cortex_a7_ex1+cortex_a7_fpadd_pipe")
 
 ;; For fconsts and fconstd, 8-bit immediate data is passed directly from
diff --git a/gcc/config/arm/cortex-a8-neon.md b/gcc/config/arm/cortex-a8-neon.md
index 57a81142a18f0c4381c13fecab07da49290b3fad..6953a9590a5c486bf4817ff2521caa299c8ecf93 100644
--- a/gcc/config/arm/cortex-a8-neon.md
+++ b/gcc/config/arm/cortex-a8-neon.md
@@ -177,7 +177,7 @@  (define_insn_reservation "cortex_a8_vfp_
 
 (define_insn_reservation "cortex_a8_vfp_cvt" 7
   (and (eq_attr "tune" "cortexa8")
-       (eq_attr "type" "f_cvt"))
+       (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
   "cortex_a8_vfp,cortex_a8_vfplite*6")
 
 ;; NEON -> core transfers.
diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md
index 4703bf36b2f8ad6a68363211f4708393924ed8a0..a66481807cf4c9263d0b565b370d6057d21a043e 100644
--- a/gcc/config/arm/cortex-a9.md
+++ b/gcc/config/arm/cortex-a9.md
@@ -233,7 +233,7 @@  (define_reservation "ca9fp_add" "ca9_iss
 
 (define_insn_reservation "cortex_a9_fadd" 4
   (and (eq_attr "tune" "cortexa9")
-       (eq_attr "type" "fadds, faddd, f_cvt"))
+       (eq_attr "type" "fadds, faddd, f_cvt, f_cvtf2i, f_cvti2f"))
   "ca9fp_add")
 
 (define_insn_reservation "cortex_a9_fcmp" 1
diff --git a/gcc/config/arm/cortex-m4-fpu.md b/gcc/config/arm/cortex-m4-fpu.md
index f148e9dba798177a105df6a36e188d3dff7b890e..81c12b74f65cf6fe113b77cb4368af5383916c44 100644
--- a/gcc/config/arm/cortex-m4-fpu.md
+++ b/gcc/config/arm/cortex-m4-fpu.md
@@ -77,7 +77,7 @@  (define_insn_reservation "cortex_m4_f_fl
 
 (define_insn_reservation "cortex_m4_f_cvt" 2
   (and (eq_attr "tune" "cortexm4")
-       (eq_attr "type" "f_cvt"))
+       (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
   "cortex_m4_ex_v")
 
 (define_insn_reservation "cortex_m4_f_load" 2
diff --git a/gcc/config/arm/cortex-r4f.md b/gcc/config/arm/cortex-r4f.md
index 8262ccd5b659a64c2dcf7b02e277188657c5164e..06e061e2b1451afcd7207186a2875cc2da3c771c 100644
--- a/gcc/config/arm/cortex-r4f.md
+++ b/gcc/config/arm/cortex-r4f.md
@@ -146,7 +146,7 @@  (define_insn_reservation "cortex_r4_fcmp
 
 (define_insn_reservation "cortex_r4_f_cvt" 8
  (and (eq_attr "tune_cortexr4" "yes")
-      (eq_attr "type" "f_cvt"))
+      (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
  "cortex_r4_single_issue*3")
 
 (define_insn_reservation "cortex_r4_f_memd" 8
diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md
index f6e4e011c338a898ed7b0b4706966755f24bd6ac..d9cf8d4b6b57967be185bcb5f9be0b4f6e2faf9a 100644
--- a/gcc/config/arm/marvell-pj4.md
+++ b/gcc/config/arm/marvell-pj4.md
@@ -209,7 +209,8 @@  (define_bypass 5 "pj4_vfp_mac" "pj4_vfp_
 (define_insn_reservation "pj4_vfp_cpy"  4
   (and (eq_attr "tune" "marvell_pj4")
        (eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,\
-                        fcmps,fcmpd,f_cvt"))  "pj4_is,nothing*2,vissue,vfast,nothing*2")
+                        fcmps,fcmpd,f_cvt,f_cvtf2i,f_cvti2f"))
+"pj4_is,nothing*2,vissue,vfast,nothing*2")
 
 ;; Enlarge latency, and wish that more nondependent insns are
 ;; scheduled immediately after VFP load.
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index ed2522b0cfef29e21c2bd9037962482ff2065f17..de817634ec98c4c568ade6d1e3d5a8910d886075 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -55,7 +55,9 @@ 
 ; clz                count leading zeros (CLZ).
 ; csel               From ARMv8-A: conditional select.
 ; extend             extend instruction (SXTB, SXTH, UXTB, UXTH).
-; f_cvt              conversion between float and integral.
+; f_cvt              conversion between float representations.
+; f_cvtf2i           conversion between float and integral types.
+; f_cvti2f           conversion between integral and float types.
 ; f_flag             transfer of co-processor flags to the CPSR.
 ; f_load[d,s]        double/single load from memory.  Used for VFP unit.
 ; f_mcr              transfer arm to vfp reg.
@@ -311,6 +313,8 @@  (define_attr "type"
   csel,\
   extend,\
   f_cvt,\
+  f_cvtf2i,\
+  f_cvti2f,\
   f_flag,\
   f_loadd,\
   f_loads,\
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 419a78984b8200f61c7ad4a88e15f5faa4078620..0e61c6eff004cf764d4fd801a508049f18a1e09f 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -991,7 +991,7 @@  (define_insn "*truncsisf2_vfp"
   "ftosizs%?\\t%0, %1"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "type" "f_cvt")]
+   (set_attr "type" "f_cvtf2i")]
 )
 
 (define_insn "*truncsidf2_vfp"
@@ -1001,7 +1001,7 @@  (define_insn "*truncsidf2_vfp"
   "ftosizd%?\\t%0, %P1"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "type" "f_cvt")]
+   (set_attr "type" "f_cvtf2i")]
 )
 
 
@@ -1012,7 +1012,7 @@  (define_insn "fixuns_truncsfsi2"
   "ftouizs%?\\t%0, %1"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "type" "f_cvt")]
+   (set_attr "type" "f_cvtf2i")]
 )
 
 (define_insn "fixuns_truncdfsi2"
@@ -1022,7 +1022,7 @@  (define_insn "fixuns_truncdfsi2"
   "ftouizd%?\\t%0, %P1"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "type" "f_cvt")]
+   (set_attr "type" "f_cvtf2i")]
 )
 
 
@@ -1033,7 +1033,7 @@  (define_insn "*floatsisf2_vfp"
   "fsitos%?\\t%0, %1"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "type" "f_cvt")]
+   (set_attr "type" "f_cvti2f")]
 )
 
 (define_insn "*floatsidf2_vfp"
@@ -1043,7 +1043,7 @@  (define_insn "*floatsidf2_vfp"
   "fsitod%?\\t%P0, %1"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "type" "f_cvt")]
+   (set_attr "type" "f_cvti2f")]
 )
 
 
@@ -1054,7 +1054,7 @@  (define_insn "floatunssisf2"
   "fuitos%?\\t%0, %1"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "type" "f_cvt")]
+   (set_attr "type" "f_cvti2f")]
 )
 
 (define_insn "floatunssidf2"
@@ -1064,7 +1064,7 @@  (define_insn "floatunssidf2"
   "fuitod%?\\t%P0, %1"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "type" "f_cvt")]
+   (set_attr "type" "f_cvti2f")]
 )
 
 
@@ -1229,7 +1229,7 @@  (define_insn "*combine_vcvt_f32_<FCVTI32
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
   "vcvt.f32.<FCVTI32typename>\\t%0, %1, %v2"
  [(set_attr "predicable" "no")
-  (set_attr "type" "f_cvt")]
+  (set_attr "type" "f_cvti2f")]
 )
 
 ;; Not the ideal way of implementing this. Ideally we would be able to split
@@ -1246,7 +1246,7 @@  (define_insn "*combine_vcvt_f64_<FCVTI32
   vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
   vmov.f64\\t%P0, %1, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
  [(set_attr "predicable" "no")
-  (set_attr "type" "f_cvt")
+  (set_attr "type" "f_cvti2f")
   (set_attr "length" "8")]
 )
 
diff --git a/gcc/config/arm/vfp11.md b/gcc/config/arm/vfp11.md
index 9e6ba849a718c7577006d9aad545fd26b0392107..3cc343e0186d3d64b4f43360a5d94c0429706efa 100644
--- a/gcc/config/arm/vfp11.md
+++ b/gcc/config/arm/vfp11.md
@@ -56,7 +56,8 @@  (define_insn_reservation "vfp_ffarith" 4
 
 (define_insn_reservation "vfp_farith" 8
  (and (eq_attr "generic_vfp" "yes")
-      (eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,fmuls,fmacs,ffmas"))
+      (eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,f_cvtf2i,f_cvti2f,\
+                       fmuls,fmacs,ffmas"))
  "fmac")
 
 (define_insn_reservation "vfp_fmul" 9