From patchwork Fri Sep 6 13:04:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_Bie=C3=9Fmann?= X-Patchwork-Id: 273188 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DCCD52C00F9 for ; Fri, 6 Sep 2013 23:05:44 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 27E1A4A090; Fri, 6 Sep 2013 15:05:23 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FruovGa6uu2i; Fri, 6 Sep 2013 15:05:22 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 653314A0D0; Fri, 6 Sep 2013 15:04:41 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 36C924A0A5 for ; Fri, 6 Sep 2013 15:04:35 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id samCFhvcjcWQ for ; Fri, 6 Sep 2013 15:04:34 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-bk0-f45.google.com (mail-bk0-f45.google.com [209.85.214.45]) by theia.denx.de (Postfix) with ESMTPS id 2826D4A0C9 for ; Fri, 6 Sep 2013 15:04:04 +0200 (CEST) Received: by mail-bk0-f45.google.com with SMTP id mx11so1280970bkb.4 for ; Fri, 06 Sep 2013 06:04:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=NmwC3tksVEEZunJ/GG6rEljv0bkuBlq/2DfRpSjbPqI=; b=xkR59I4ewo8Nogc7yA6Wv6mcYlaUGDOLuYswJVfw3rxmTKJHBHyHOiGbaUzyLTQdIg nZs9XXGz5cU1mlq9rjq7qEU60wqJ4ZBhm92kgJwSrmqZ5/1c7sireBWqbmywA/46KST/ CIQcR8gtsOIZK9CxJWd4heeExSiVYgUKjz1XXAR7tVk3TND78Z/ory1woOwYx8otbx+R XSSbtISJh/fBRGDHFUGJTzWbiefE4NvXocJp3xK/8FKEDArd57b7HfnZod7LPTJdXuP4 X7JNLtlBRCXoXj3v8yzmLrqcp3C2EOySP5U7tY2CT7lAwKwNQRjB3PrsE0m6OZ/ngauo C0tg== X-Received: by 10.205.86.199 with SMTP id at7mr2315047bkc.9.1378472644109; Fri, 06 Sep 2013 06:04:04 -0700 (PDT) Received: from localhost ([2a01:198:47b:1:210:75ff:fe1a:cd1e]) by mx.google.com with ESMTPSA id nv4sm680383bkb.3.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 06 Sep 2013 06:04:03 -0700 (PDT) From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= To: u-boot@lists.denx.de Date: Fri, 6 Sep 2013 15:04:58 +0200 Message-Id: <1378472698-18557-13-git-send-email-andreas.devel@googlemail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1378472698-18557-1-git-send-email-andreas.devel@googlemail.com> References: <1378472698-18557-1-git-send-email-andreas.devel@googlemail.com> MIME-Version: 1.0 Cc: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= , Thomas Weber Subject: [U-Boot] [PATCH 13/13] tricorder: support 256MiB SDRAM on revision > D X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Andreas Bießmann Signed-off-by: Andreas Bießmann --- board/corscience/tricorder/tricorder.c | 45 +++++++++++++++++++++++++++----- include/configs/tricorder.h | 2 +- 2 files changed, 39 insertions(+), 8 deletions(-) diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index fb5d036..2dfcb27 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -154,12 +154,43 @@ int board_mmc_init(bd_t *bis) */ void get_board_mem_timings(struct board_sdrc_timings *timings) { - /* General SDRC config */ - timings->mcfg = MICRON_V_MCFG_165(128 << 20); - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + struct tricorder_eeprom eeprom; + get_eeprom(&eeprom); - /* AC timings */ - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->mr = MICRON_V_MR_165; + /* General SDRC config */ + if (eeprom.board_version[0] > 'D') { + /* use optimized timings for our SDRAM device */ + timings->mcfg = MCFG((256 << 20), 14); +#define MT46H64M32_TDAL 6 /* Twr/Tck + Trp/tck */ + /* 15/6 + 18/6 = 5.5 -> 6 */ +#define MT46H64M32_TDPL 3 /* 15/6 = 2.5 -> 3 (Twr) */ +#define MT46H64M32_TRRD 2 /* 12/6 = 2 */ +#define MT46H64M32_TRCD 3 /* 18/6 = 3 */ +#define MT46H64M32_TRP 3 /* 18/6 = 3 */ +#define MT46H64M32_TRAS 7 /* 42/6 = 7 */ +#define MT46H64M32_TRC 10 /* 60/6 = 10 */ +#define MT46H64M32_TRFC 12 /* 72/6 = 12 */ + timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC, + MT46H64M32_TRAS, MT46H64M32_TRP, + MT46H64M32_TRCD, MT46H64M32_TRRD, + MT46H64M32_TDPL, + MT46H64M32_TDAL); + +#define MT46H64M32_TWTR 1 +#define MT46H64M32_TCKE 1 +#define MT46H64M32_XSR 19 /* 112.5/6 = 18.75 => ~19 */ +#define MT46H64M32_TXP 1 + timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE, + MT46H64M32_TXP, MT46H64M32_XSR); + + timings->mr = MICRON_V_MR_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } else { + /* use conservative beagleboard timings as default */ + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->mr = MICRON_V_MR_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } } diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 7eff448..608af03 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -354,7 +354,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#define CONFIG_SPL_MAX_SIZE (55 * 1024) /* 7 KB for stack */ +#define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/