From patchwork Fri Sep 6 09:30:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ying.zhang@freescale.com X-Patchwork-Id: 273145 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B4F5E2C00FF for ; Fri, 6 Sep 2013 20:36:06 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 866FE4A064; Fri, 6 Sep 2013 12:35:56 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id acf1DUA7+JoT; Fri, 6 Sep 2013 12:35:56 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5CB564A08D; Fri, 6 Sep 2013 12:35:37 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A10A64A05E for ; Fri, 6 Sep 2013 12:35:30 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YKRarA4dD2Hj for ; Fri, 6 Sep 2013 12:35:24 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from db9outboundpool.messaging.microsoft.com (mail-db9lp0253.outbound.messaging.microsoft.com [213.199.154.253]) by theia.denx.de (Postfix) with ESMTPS id 4087C4A063 for ; Fri, 6 Sep 2013 12:35:17 +0200 (CEST) Received: from mail7-db9-R.bigfish.com (10.174.16.232) by DB9EHSOBE002.bigfish.com (10.174.14.65) with Microsoft SMTP Server id 14.1.225.22; Fri, 6 Sep 2013 10:35:14 +0000 Received: from mail7-db9 (localhost [127.0.0.1]) by mail7-db9-R.bigfish.com (Postfix) with ESMTP id D7D6B900151 for ; Fri, 6 Sep 2013 10:35:14 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h1de097h8275bhz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h1354h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h1155h) Received: from mail7-db9 (localhost.localdomain [127.0.0.1]) by mail7-db9 (MessageSwitch) id 1378463712379777_21997; Fri, 6 Sep 2013 10:35:12 +0000 (UTC) Received: from DB9EHSMHS002.bigfish.com (unknown [10.174.16.235]) by mail7-db9.bigfish.com (Postfix) with ESMTP id 4E7CCA00041 for ; Fri, 6 Sep 2013 10:35:12 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB9EHSMHS002.bigfish.com (10.174.14.12) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 6 Sep 2013 10:35:11 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.3.158.2; Fri, 6 Sep 2013 10:35:10 +0000 Received: from localhost.localdomain (tank.ap.freescale.net [10.193.20.104]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r86AZ2AX022191; Fri, 6 Sep 2013 03:35:08 -0700 From: To: Date: Fri, 6 Sep 2013 17:30:58 +0800 Message-ID: <1378459858-5176-3-git-send-email-ying.zhang@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1378459858-5176-1-git-send-email-ying.zhang@freescale.com> References: <1378459858-5176-1-git-send-email-ying.zhang@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: scottwood@freescale.com, R58495@freescale.com, X.Xie@freescale.com, Ying Zhang Subject: [U-Boot] [PATCH 3/3] powerpc: p1_p2_rdb_pc: add TPL for p1_p2_rdb_pc nand boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Ying Zhang Enable TPL for p1_p2_rdb_pc nand boot. Signed-off-by: Ying Zhang --- board/freescale/p1_p2_rdb_pc/spl.c | 15 +++++ board/freescale/p1_p2_rdb_pc/spl_minimal.c | 83 ++-------------------------- board/freescale/p1_p2_rdb_pc/tlb.c | 8 ++- include/configs/p1_p2_rdb_pc.h | 83 +++++++++++++++++++--------- 4 files changed, 84 insertions(+), 105 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 07fab46..9bb0716 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -83,12 +83,21 @@ void board_init_r(gd_t *gd, ulong dest_addr) mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); +#ifndef CONFIG_SPL_NAND_BOOT env_init(); +#endif #ifdef CONFIG_SPL_MMC_BOOT mmc_initialize(bd); #endif /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#else env_relocate(); +#endif #ifdef CONFIG_SYS_I2C i2c_init_all(); @@ -97,11 +106,17 @@ void board_init_r(gd_t *gd, ulong dest_addr) #endif gd->ram_size = initdram(0); +#ifdef CONFIG_SPL_NAND_BOOT + puts("Tertiary program loader running in sram..."); +#else puts("Second program loader running in sram...\n"); +#endif #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); #elif defined(CONFIG_SPL_SPI_BOOT) spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); #endif } diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index ac07572..adfa7b1 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -15,59 +15,14 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SYS_INIT_L2_ADDR -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -static void sdram_init(void) -{ - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); -#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); - __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); -#endif - __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); - - __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); - - __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); - - __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); - - /* Set, but do not enable the memory */ - __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); - - asm volatile("sync;isync"); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); - - set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); -} -#endif - void board_init_f(ulong bootflag) { u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; -#ifndef CONFIG_QE - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); -#elif defined(CONFIG_P1021RDB) - par_io_t *par_io = (par_io_t *)&(gur->qe_par_io); + +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); #endif /* initialize selected port with appropriate baud rate */ @@ -80,35 +35,6 @@ void board_init_f(ulong bootflag) puts("\nNAND boot... "); -#ifndef CONFIG_QE - /* init DDR3 reset signal */ - __raw_writel(0x02000000, &pgpio->gpdir); - __raw_writel(0x00200000, &pgpio->gpodr); - __raw_writel(0x00000000, &pgpio->gpdat); - udelay(1000); - __raw_writel(0x00200000, &pgpio->gpdat); - udelay(1000); - __raw_writel(0x00000000, &pgpio->gpdir); -#elif defined(CONFIG_P1021RDB) - /* init DDR3 reset signal CE_PB8 */ - out_be32(&par_io[1].cpdir1, 0x00004000); - out_be32(&par_io[1].cpodr, 0x00800000); - out_be32(&par_io[1].cppar1, 0x00000000); - /* reset DDR3 */ - out_be32(&par_io[1].cpdat, 0x00800000); - udelay(1000); - out_be32(&par_io[1].cpdat, 0x00000000); - udelay(1000); - out_be32(&par_io[1].cpdat, 0x00800000); - /* disable the CE_PB8 */ - out_be32(&par_io[1].cpdir1, 0x00000000); -#endif - -#ifndef CONFIG_SYS_INIT_L2_ADDR - /* Initialize the DDR3 */ - sdram_init(); -#endif - /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. @@ -118,6 +44,7 @@ void board_init_f(ulong bootflag) void board_init_r(gd_t *gd, ulong dest_addr) { + puts("\nSecond program loader running in sram..."); nand_boot(); } diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index d6afa7b..1c0008b 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -98,7 +98,13 @@ struct fsl_e_tlb_entry tlb_table[] = { /* *I*G - L2SRAM */ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 11, BOOKE_PAGESZ_256K, 1) + 0, 11, BOOKE_PAGESZ_256K, 1), +#if CONFIG_SYS_L2_SIZE >= (256 << 10) + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_256K, 1) +#endif #endif }; diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 35d6746..a435f29 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -205,36 +205,45 @@ #ifdef CONFIG_NAND #define CONFIG_SPL +#define CONFIG_TPL +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_NAND_BOOT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NAND_INIT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SPL_MAX_SIZE (128 << 10) +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#elif defined(CONFIG_SPL_BUILD) #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SPL_TEXT_BASE 0xfffff000 +#define CONFIG_SPL_TEXT_BASE 0xff800000 #define CONFIG_SPL_MAX_SIZE 4096 - -#ifdef CONFIG_SYS_INIT_L2_ADDR -/* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */ -#define CONFIG_SYS_TEXT_BASE 0xf8f82000 -#define CONFIG_SPL_RELOC_TEXT_BASE \ - (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) -#define CONFIG_SPL_RELOC_STACK \ - (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) -#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) -#define CONFIG_SYS_NAND_U_BOOT_START \ - (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE) -#else -#define CONFIG_SYS_TEXT_BASE 0x00201000 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#endif - -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif /* not CONFIG_TPL_BUILD */ + +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_TPL_PAD_TO 0x20000 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #endif #ifndef CONFIG_SYS_TEXT_BASE @@ -576,6 +585,23 @@ #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#elif defined(CONFIG_NAND) +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) +#else +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) +#endif /* CONFIG_TPL_BUILD */ #endif #endif @@ -801,9 +827,14 @@ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_NAND) -#define CONFIG_ENV_IS_IN_NAND +#ifdef CONFIG_TPL_BUILD +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#else #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (1024 * 1024) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */