From patchwork Fri Sep 6 01:45:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Yang X-Patchwork-Id: 273019 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E6AEB2C00FC for ; Fri, 6 Sep 2013 11:46:13 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758750Ab3IFBqN (ORCPT ); Thu, 5 Sep 2013 21:46:13 -0400 Received: from e28smtp02.in.ibm.com ([122.248.162.2]:34365 "EHLO e28smtp02.in.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754065Ab3IFBqM (ORCPT ); Thu, 5 Sep 2013 21:46:12 -0400 Received: from /spool/local by e28smtp02.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 6 Sep 2013 07:05:25 +0530 Received: from d28dlp02.in.ibm.com (9.184.220.127) by e28smtp02.in.ibm.com (192.168.1.132) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Fri, 6 Sep 2013 07:05:23 +0530 Received: from d28relay05.in.ibm.com (d28relay05.in.ibm.com [9.184.220.62]) by d28dlp02.in.ibm.com (Postfix) with ESMTP id 99F4D394004E for ; Fri, 6 Sep 2013 07:15:54 +0530 (IST) Received: from d28av03.in.ibm.com (d28av03.in.ibm.com [9.184.220.65]) by d28relay05.in.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r861k4xh47382776 for ; Fri, 6 Sep 2013 07:16:04 +0530 Received: from d28av03.in.ibm.com (localhost [127.0.0.1]) by d28av03.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id r861k5aT019769 for ; Fri, 6 Sep 2013 07:16:05 +0530 Received: from localhost (weiyang.cn.ibm.com [9.111.19.249]) by d28av03.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id r861k5v0019756; Fri, 6 Sep 2013 07:16:05 +0530 From: Wei Yang To: bhelgaas@google.com, linux-pci@vger.kernel.org Cc: Wei Yang Subject: [PATCH 2/3] PCI: Use spec name for the comment of PCIe capability field Date: Fri, 6 Sep 2013 09:45:57 +0800 Message-Id: <1378431958-7874-2-git-send-email-weiyang@linux.vnet.ibm.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1378431958-7874-1-git-send-email-weiyang@linux.vnet.ibm.com> References: <1378431958-7874-1-git-send-email-weiyang@linux.vnet.ibm.com> X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13090601-5816-0000-0000-000009C3C252 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org According to the PCIe specification, bit 7:4 of PCI Express Capabilities Register in a PCI Express Capability Structure is used to identify the Device/Port type. If this field equals to 0x7, this PCIe device is a PCI Express to PCI/PCI-X Bridge. While the comment of this value in the code does not comply with the specification. This patch changes the comment to "PCIE to PCI/PCI-X Bridge" instead of "PCI/PCI-X Bridge", which comply with the specification. Signed-off-by: Wei Yang --- include/uapi/linux/pci_regs.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index c3cc01d..b82b2ff 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -421,7 +421,7 @@ #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ -#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ +#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIE to PCI/PCI-X Bridge */ #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */ #define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ #define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */