Patchwork ARM: mach-imx: clk-imx51-imx53: Fix 'spdif1_pred' clock registration

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Submitter Fabio Estevam
Date Sept. 5, 2013, 7:02 p.m.
Message ID <1378407777-26546-1-git-send-email-fabio.estevam@freescale.com>
Download mbox | patch
Permalink /patch/272939/
State New
Headers show

Comments

Fabio Estevam - Sept. 5, 2013, 7:02 p.m.
Since commit beb2d1c1ba (ARM i.MX5: Add S/PDIF clocks), the following clock 
error appears on mx51:

TrustZone Interrupt Controller (TZIC) initialized
i.MX51 clk 180: register failed with -17
i.MX5 clk 180: register failed with -17
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms
CPU identified as i.MX51, silicon rev 3.0
...

Clock 180 corresponds to 'spdif1_podf' and this clock is getting registered 
twice.

Fix it, by properly registering the 'spdif1_pred' clock, which should not 
reference 'spdif1_podf'.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 arch/arm/mach-imx/clk-imx51-imx53.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Shawn Guo - Sept. 9, 2013, 2:37 p.m.
On Thu, Sep 05, 2013 at 04:02:57PM -0300, Fabio Estevam wrote:
> Since commit beb2d1c1ba (ARM i.MX5: Add S/PDIF clocks), the following clock 
> error appears on mx51:
> 
> TrustZone Interrupt Controller (TZIC) initialized
> i.MX51 clk 180: register failed with -17
> i.MX5 clk 180: register failed with -17
> sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms
> CPU identified as i.MX51, silicon rev 3.0
> ...
> 
> Clock 180 corresponds to 'spdif1_podf' and this clock is getting registered 
> twice.
> 
> Fix it, by properly registering the 'spdif1_pred' clock, which should not 
> reference 'spdif1_podf'.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Applied, thanks.

Shawn

Patch

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 1a56a33..d9094b9 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -397,7 +397,7 @@  int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 				mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
 	clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
 				spdif_sel, ARRAY_SIZE(spdif_sel));
-	clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
+	clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
 	clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
 	clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
 				mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));