@@ -935,7 +935,8 @@ static const void * const qemu_st_helpers[4] = {
return value is 0, R1 is not used. */
static int tcg_out_tlb_read(TCGContext *s, int r0, int r1, int addrlo,
- int addrhi, int s_bits, int lab_miss, int offset)
+ int addrhi, TCGMemOp s_bits, int lab_miss,
+ int offset)
{
int ret;
@@ -1020,30 +1021,27 @@ static int tcg_out_arg_reg64(TCGContext *s, int argno, TCGArg vl, TCGArg vh)
}
#endif
-static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo_reg, int datahi_reg,
- int addr_reg, int addend_reg, int opc)
+static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo_reg,
+ int datahi_reg, int addr_reg,
+ int addend_reg, TCGMemOp opc)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- const int bswap = 0;
-#else
- const int bswap = 1;
-#endif
+ const TCGMemOp bswap = opc & MO_BSWAP;
- switch (opc) {
- case 0:
+ switch (opc & MO_SSIZE) {
+ case MO_UB:
tcg_out_ldst_index(s, datalo_reg, addr_reg, addend_reg, INSN_LDBX);
break;
- case 0 | 4:
+ case MO_SB:
tcg_out_ldst_index(s, datalo_reg, addr_reg, addend_reg, INSN_LDBX);
tcg_out_ext8s(s, datalo_reg, datalo_reg);
break;
- case 1:
+ case MO_UW:
tcg_out_ldst_index(s, datalo_reg, addr_reg, addend_reg, INSN_LDHX);
if (bswap) {
tcg_out_bswap16(s, datalo_reg, datalo_reg, 0);
}
break;
- case 1 | 4:
+ case MO_SW:
tcg_out_ldst_index(s, datalo_reg, addr_reg, addend_reg, INSN_LDHX);
if (bswap) {
tcg_out_bswap16(s, datalo_reg, datalo_reg, 1);
@@ -1051,13 +1049,13 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo_reg, int datahi_reg
tcg_out_ext16s(s, datalo_reg, datalo_reg);
}
break;
- case 2:
+ case MO_UL:
tcg_out_ldst_index(s, datalo_reg, addr_reg, addend_reg, INSN_LDWX);
if (bswap) {
tcg_out_bswap32(s, datalo_reg, datalo_reg, TCG_REG_R20);
}
break;
- case 3:
+ case MO_Q:
if (bswap) {
int t = datahi_reg;
datahi_reg = datalo_reg;
@@ -1087,11 +1085,12 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo_reg, int datahi_reg
}
}
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
+static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp opc)
{
+ TCGMemOp s_bits = opc & MO_SIZE;
int datalo_reg = *args++;
/* Note that datahi_reg is only used for 64-bit loads. */
- int datahi_reg = (opc == 3 ? *args++ : TCG_REG_R0);
+ int datahi_reg = (s_bits == MO_64 ? *args++ : TCG_REG_R0);
int addrlo_reg = *args++;
#if defined(CONFIG_SOFTMMU)
@@ -1105,7 +1104,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_read);
offset = tcg_out_tlb_read(s, TCG_REG_R26, TCG_REG_R25, addrlo_reg,
- addrhi_reg, opc & 3, lab1, offset);
+ addrhi_reg, s_bits, lab1, offset);
/* TLB Hit. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R20,
@@ -1128,26 +1127,26 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
}
argno = tcg_out_arg_reg32(s, argno, mem_index, true);
- tcg_out_call(s, qemu_ld_helpers[opc & 3]);
+ tcg_out_call(s, qemu_ld_helpers[s_bits]);
- switch (opc) {
- case 0:
+ switch (opc & MO_SSIZE) {
+ case MO_UB:
tcg_out_andi(s, datalo_reg, TCG_REG_RET0, 0xff);
break;
- case 0 | 4:
+ case MO_SB:
tcg_out_ext8s(s, datalo_reg, TCG_REG_RET0);
break;
- case 1:
+ case MO_UW:
tcg_out_andi(s, datalo_reg, TCG_REG_RET0, 0xffff);
break;
- case 1 | 4:
+ case MO_SW:
tcg_out_ext16s(s, datalo_reg, TCG_REG_RET0);
break;
- case 2:
- case 2 | 4:
+ case MO_UL:
+ case MO_SL:
tcg_out_mov(s, TCG_TYPE_I32, datalo_reg, TCG_REG_RET0);
break;
- case 3:
+ case MO_Q:
tcg_out_mov(s, TCG_TYPE_I32, datahi_reg, TCG_REG_RET0);
tcg_out_mov(s, TCG_TYPE_I32, datalo_reg, TCG_REG_RET1);
break;
@@ -1164,33 +1163,29 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
}
static void tcg_out_qemu_st_direct(TCGContext *s, int datalo_reg,
- int datahi_reg, int addr_reg, int opc)
+ int datahi_reg, int addr_reg, TCGMemOp opc)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- const int bswap = 0;
-#else
- const int bswap = 1;
-#endif
+ const TCGMemOp bswap = opc & MO_BSWAP;
- switch (opc) {
- case 0:
+ switch (opc & MO_SIZE) {
+ case MO_8:
tcg_out_ldst(s, datalo_reg, addr_reg, 0, INSN_STB);
break;
- case 1:
+ case MO_16:
if (bswap) {
tcg_out_bswap16(s, TCG_REG_R20, datalo_reg, 0);
datalo_reg = TCG_REG_R20;
}
tcg_out_ldst(s, datalo_reg, addr_reg, 0, INSN_STH);
break;
- case 2:
+ case MO_32:
if (bswap) {
tcg_out_bswap32(s, TCG_REG_R20, datalo_reg, TCG_REG_R20);
datalo_reg = TCG_REG_R20;
}
tcg_out_ldst(s, datalo_reg, addr_reg, 0, INSN_STW);
break;
- case 3:
+ case MO_64:
if (bswap) {
tcg_out_bswap32(s, TCG_REG_R20, datalo_reg, TCG_REG_R20);
tcg_out_bswap32(s, TCG_REG_R23, datahi_reg, TCG_REG_R23);
@@ -1206,11 +1201,12 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo_reg,
}
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
+static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp opc)
{
+ TCGMemOp s_bits = opc & MO_SIZE;
int datalo_reg = *args++;
/* Note that datahi_reg is only used for 64-bit loads. */
- int datahi_reg = (opc == 3 ? *args++ : TCG_REG_R0);
+ int datahi_reg = (s_bits == MO_64 ? *args++ : TCG_REG_R0);
int addrlo_reg = *args++;
#if defined(CONFIG_SOFTMMU)
@@ -1224,7 +1220,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
offset = tcg_out_tlb_read(s, TCG_REG_R26, TCG_REG_R25, addrlo_reg,
- addrhi_reg, opc, lab1, offset);
+ addrhi_reg, s_bits, lab1, offset);
/* TLB Hit. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R20,
@@ -1250,19 +1246,19 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
}
next = (argno < 4 ? tcg_target_call_iarg_regs[argno] : TCG_REG_R20);
- switch(opc) {
- case 0:
+ switch (s_bits) {
+ case MO_8:
tcg_out_andi(s, next, datalo_reg, 0xff);
argno = tcg_out_arg_reg32(s, argno, next, false);
break;
- case 1:
+ case MO_16:
tcg_out_andi(s, next, datalo_reg, 0xffff);
argno = tcg_out_arg_reg32(s, argno, next, false);
break;
- case 2:
+ case MO_32:
argno = tcg_out_arg_reg32(s, argno, datalo_reg, false);
break;
- case 3:
+ case MO_64:
argno = tcg_out_arg_reg64(s, argno, datalo_reg, datahi_reg);
break;
default:
@@ -1270,7 +1266,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
}
argno = tcg_out_arg_reg32(s, argno, mem_index, true);
- tcg_out_call(s, qemu_st_helpers[opc]);
+ tcg_out_call(s, qemu_st_helpers[s_bits]);
/* label2: */
tcg_out_label(s, lab2, s->code_ptr);
@@ -1534,35 +1530,35 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
case INDEX_op_qemu_ld8u:
- tcg_out_qemu_ld(s, args, 0);
+ tcg_out_qemu_ld(s, args, MO_UB);
break;
case INDEX_op_qemu_ld8s:
- tcg_out_qemu_ld(s, args, 0 | 4);
+ tcg_out_qemu_ld(s, args, MO_SB);
break;
case INDEX_op_qemu_ld16u:
- tcg_out_qemu_ld(s, args, 1);
+ tcg_out_qemu_ld(s, args, MO_TEUW);
break;
case INDEX_op_qemu_ld16s:
- tcg_out_qemu_ld(s, args, 1 | 4);
+ tcg_out_qemu_ld(s, args, MO_TESW);
break;
case INDEX_op_qemu_ld32:
- tcg_out_qemu_ld(s, args, 2);
+ tcg_out_qemu_ld(s, args, MO_TEUL);
break;
case INDEX_op_qemu_ld64:
- tcg_out_qemu_ld(s, args, 3);
+ tcg_out_qemu_ld(s, args, MO_TEQ);
break;
case INDEX_op_qemu_st8:
- tcg_out_qemu_st(s, args, 0);
+ tcg_out_qemu_st(s, args, MO_UB);
break;
case INDEX_op_qemu_st16:
- tcg_out_qemu_st(s, args, 1);
+ tcg_out_qemu_st(s, args, MO_TEUW);
break;
case INDEX_op_qemu_st32:
- tcg_out_qemu_st(s, args, 2);
+ tcg_out_qemu_st(s, args, MO_TEUL);
break;
case INDEX_op_qemu_st64:
- tcg_out_qemu_st(s, args, 3);
+ tcg_out_qemu_st(s, args, MO_TEQ);
break;
default:
Untested. Signed-off-by: Richard Henderson <rth@twiddle.net> --- tcg/hppa/tcg-target.c | 110 ++++++++++++++++++++++++-------------------------- 1 file changed, 53 insertions(+), 57 deletions(-)