From patchwork Wed Sep 4 09:05:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 272536 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E2B6A2C00BC for ; Wed, 4 Sep 2013 19:31:25 +1000 (EST) Received: from localhost ([::1]:51402 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VH9Qp-0008LW-PR for incoming@patchwork.ozlabs.org; Wed, 04 Sep 2013 05:31:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49951) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VH92J-0004hb-D5 for qemu-devel@nongnu.org; Wed, 04 Sep 2013 05:06:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VH927-00080A-Cc for qemu-devel@nongnu.org; Wed, 04 Sep 2013 05:06:03 -0400 Received: from cantor2.suse.de ([195.135.220.15]:45496 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VH926-0007zj-Mo for qemu-devel@nongnu.org; Wed, 04 Sep 2013 05:05:51 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 49C7CA53AC; Wed, 4 Sep 2013 11:05:50 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2013 11:05:16 +0200 Message-Id: <1378285521-3230-37-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1378285521-3230-1-git-send-email-afaerber@suse.de> References: <1378285521-3230-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: Michael Walle , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [RFC qom-cpu 36/41] target-lm32: Replace DisasContext::env field with LM32CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This cleans up some lm32_env_get_cpu() introduced for cpu_abort(). Signed-off-by: Andreas Färber --- target-lm32/translate.c | 60 ++++++++++++++++++++++++------------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 532345b..57b91c4 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -64,7 +64,7 @@ enum { /* This is the state at translation time. */ typedef struct DisasContext { - CPULM32State *env; + LM32CPU *cpu; target_ulong pc; /* Decoder. */ @@ -421,8 +421,8 @@ static void dec_divu(DisasContext *dc) LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1); - if (!(dc->env->features & LM32_FEATURE_DIVIDE)) { - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware divider is not available\n"); + if (!(dc->cpu->env.features & LM32_FEATURE_DIVIDE)) { + cpu_abort(CPU(dc->cpu), "hardware divider is not available\n"); } l1 = gen_new_label(); @@ -499,8 +499,8 @@ static void dec_modu(DisasContext *dc) LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1); - if (!(dc->env->features & LM32_FEATURE_DIVIDE)) { - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware divider is not available\n"); + if (!(dc->cpu->env.features & LM32_FEATURE_DIVIDE)) { + cpu_abort(CPU(dc->cpu), "hardware divider is not available\n"); } l1 = gen_new_label(); @@ -520,8 +520,8 @@ static void dec_mul(DisasContext *dc) LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1); } - if (!(dc->env->features & LM32_FEATURE_MULTIPLY)) { - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware multiplier is not available\n"); + if (!(dc->cpu->env.features & LM32_FEATURE_MULTIPLY)) { + cpu_abort(CPU(dc->cpu), "hardware multiplier is not available\n"); } if (dc->format == OP_FMT_RI) { @@ -590,7 +590,7 @@ static void dec_scall(DisasContext *dc) } else if (dc->imm5 == 2) { LOG_DIS("break\n"); } else { - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid opcode\n"); + cpu_abort(CPU(dc->cpu), "invalid opcode\n"); } if (dc->imm5 == 7) { @@ -647,10 +647,10 @@ static void dec_rcsr(DisasContext *dc) case CSR_WP1: case CSR_WP2: case CSR_WP3: - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid read access csr=%x\n", dc->csr); + cpu_abort(CPU(dc->cpu), "invalid read access csr=%x\n", dc->csr); break; default: - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "read_csr: unknown csr=%x\n", dc->csr); + cpu_abort(CPU(dc->cpu), "read_csr: unknown csr=%x\n", dc->csr); break; } } @@ -671,8 +671,8 @@ static void dec_sextb(DisasContext *dc) { LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0); - if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) { - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware sign extender is not available\n"); + if (!(dc->cpu->env.features & LM32_FEATURE_SIGN_EXTEND)) { + cpu_abort(CPU(dc->cpu), "hardware sign extender is not available\n"); } tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]); @@ -682,8 +682,8 @@ static void dec_sexth(DisasContext *dc) { LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0); - if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) { - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware sign extender is not available\n"); + if (!(dc->cpu->env.features & LM32_FEATURE_SIGN_EXTEND)) { + cpu_abort(CPU(dc->cpu), "hardware sign extender is not available\n"); } tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]); @@ -709,8 +709,8 @@ static void dec_sl(DisasContext *dc) LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1); } - if (!(dc->env->features & LM32_FEATURE_SHIFT)) { - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter is not available\n"); + if (!(dc->cpu->env.features & LM32_FEATURE_SHIFT)) { + cpu_abort(CPU(dc->cpu), "hardware shifter is not available\n"); } if (dc->format == OP_FMT_RI) { @@ -731,12 +731,12 @@ static void dec_sr(DisasContext *dc) LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1); } - if (!(dc->env->features & LM32_FEATURE_SHIFT)) { + if (!(dc->cpu->env.features & LM32_FEATURE_SHIFT)) { if (dc->format == OP_FMT_RI) { /* TODO: check r1 == 1 during runtime */ } else { if (dc->imm5 != 1) { - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter is not available\n"); + cpu_abort(CPU(dc->cpu), "hardware shifter is not available\n"); } } } @@ -759,12 +759,12 @@ static void dec_sru(DisasContext *dc) LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1); } - if (!(dc->env->features & LM32_FEATURE_SHIFT)) { + if (!(dc->cpu->env.features & LM32_FEATURE_SHIFT)) { if (dc->format == OP_FMT_RI) { /* TODO: check r1 == 1 during runtime */ } else { if (dc->imm5 != 1) { - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter is not available\n"); + cpu_abort(CPU(dc->cpu), "hardware shifter is not available\n"); } } } @@ -802,7 +802,7 @@ static void dec_user(DisasContext *dc) { LOG_DIS("user"); - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "user insn undefined\n"); + cpu_abort(CPU(dc->cpu), "user insn undefined\n"); } static void dec_wcsr(DisasContext *dc) @@ -867,8 +867,8 @@ static void dec_wcsr(DisasContext *dc) case CSR_BP2: case CSR_BP3: no = dc->csr - CSR_BP0; - if (dc->env->num_bps <= no) { - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "breakpoint #%i is not available\n", no); + if (dc->cpu->env.num_bps <= no) { + cpu_abort(CPU(dc->cpu), "breakpoint #%i is not available\n", no); } tcg_gen_mov_tl(cpu_bp[no], cpu_R[dc->r1]); break; @@ -877,17 +877,17 @@ static void dec_wcsr(DisasContext *dc) case CSR_WP2: case CSR_WP3: no = dc->csr - CSR_WP0; - if (dc->env->num_wps <= no) { - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "watchpoint #%i is not available\n", no); + if (dc->cpu->env.num_wps <= no) { + cpu_abort(CPU(dc->cpu), "watchpoint #%i is not available\n", no); } tcg_gen_mov_tl(cpu_wp[no], cpu_R[dc->r1]); break; case CSR_CC: case CSR_CFG: - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid write access csr=%x\n", dc->csr); + cpu_abort(CPU(dc->cpu), "invalid write access csr=%x\n", dc->csr); break; default: - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "write_csr unknown csr=%x\n", dc->csr); + cpu_abort(CPU(dc->cpu), "write_csr unknown csr=%x\n", dc->csr); break; } } @@ -933,7 +933,7 @@ static void dec_xor(DisasContext *dc) static void dec_ill(DisasContext *dc) { - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "unknown opcode 0x%02x\n", dc->opcode); + cpu_abort(CPU(dc->cpu), "unknown opcode 0x%02x\n", dc->opcode); } typedef void (*DecoderInfo)(DisasContext *dc); @@ -967,7 +967,7 @@ static inline void decode(DisasContext *dc, uint32_t ir) LOG_DIS("nr_nops=%d\t", dc->nr_nops); dc->nr_nops++; if (dc->nr_nops > 4) { - cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "fetching nop sequence\n"); + cpu_abort(CPU(dc->cpu), "fetching nop sequence\n"); } } @@ -1027,7 +1027,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu, int max_insns; pc_start = tb->pc; - dc->env = env; + dc->cpu = cpu; dc->tb = tb; gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;