From patchwork Wed Sep 4 09:05:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 272526 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id F01BC2C008C for ; Wed, 4 Sep 2013 19:25:10 +1000 (EST) Received: from localhost ([::1]:51349 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VH9Km-0007gG-Vr for incoming@patchwork.ozlabs.org; Wed, 04 Sep 2013 05:25:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49876) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VH92D-0004Y1-Oi for qemu-devel@nongnu.org; Wed, 04 Sep 2013 05:06:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VH923-0007yB-Va for qemu-devel@nongnu.org; Wed, 04 Sep 2013 05:05:57 -0400 Received: from cantor2.suse.de ([195.135.220.15]:45458 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VH923-0007xJ-Ac; Wed, 04 Sep 2013 05:05:47 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id DED60A5443; Wed, 4 Sep 2013 11:05:46 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2013 11:05:06 +0200 Message-Id: <1378285521-3230-27-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1378285521-3230-1-git-send-email-afaerber@suse.de> References: <1378285521-3230-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: "open list:PowerPC" , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Alexander Graf Subject: [Qemu-devel] [RFC qom-cpu 26/41] target-ppc: Use PowerPCCPU in PowerPCCPUClass::handle_mmu_fault hook X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Andreas Färber --- target-ppc/cpu-qom.h | 8 +++++--- target-ppc/mmu-hash32.c | 5 +++-- target-ppc/mmu-hash32.h | 2 +- target-ppc/mmu-hash64.c | 5 +++-- target-ppc/mmu-hash64.h | 2 +- target-ppc/mmu_helper.c | 2 +- 6 files changed, 14 insertions(+), 10 deletions(-) diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index f3c710a..c213589 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -38,6 +38,8 @@ #define POWERPC_CPU_GET_CLASS(obj) \ OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU) +typedef struct PowerPCCPU PowerPCCPU; + /** * PowerPCCPUClass: * @parent_realize: The parent class' realize handler. @@ -70,7 +72,7 @@ typedef struct PowerPCCPUClass { void (*init_proc)(CPUPPCState *env); int (*check_pow)(CPUPPCState *env); #if defined(CONFIG_SOFTMMU) - int (*handle_mmu_fault)(CPUPPCState *env, target_ulong eaddr, int rwx, + int (*handle_mmu_fault)(PowerPCCPU *cpu, target_ulong eaddr, int rwx, int mmu_idx); #endif } PowerPCCPUClass; @@ -81,13 +83,13 @@ typedef struct PowerPCCPUClass { * * A PowerPC CPU. */ -typedef struct PowerPCCPU { +struct PowerPCCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ CPUPPCState env; -} PowerPCCPU; +}; static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) { diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index aa87084..6a4d6a8 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -381,10 +381,11 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte, return (rpn & ~mask) | (eaddr & mask); } -int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, int mmu_idx) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = CPU(cpu); + CPUPPCState *env = &cpu->env; target_ulong sr; hwaddr pte_offset; ppc_hash_pte32_t pte; diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h index 884786b..4a49ceb 100644 --- a/target-ppc/mmu-hash32.h +++ b/target-ppc/mmu-hash32.h @@ -5,7 +5,7 @@ hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash); hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr); -int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw, int mmu_idx); /* diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 04dcfb3..82bfa7c 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -396,10 +396,11 @@ static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte, return (rpn & ~mask) | (eaddr & mask); } -int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, +int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, int mmu_idx) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = CPU(cpu); + CPUPPCState *env = &cpu->env; ppc_slb_t *slb; hwaddr pte_offset; ppc_hash_pte64_t pte; diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h index 55f5a23..41b0ac4 100644 --- a/target-ppc/mmu-hash64.h +++ b/target-ppc/mmu-hash64.h @@ -7,7 +7,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs); hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr); -int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, +int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw, int mmu_idx); #endif diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index e214316..5a237ce 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -2901,7 +2901,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, int ret; if (pcc->handle_mmu_fault) { - ret = pcc->handle_mmu_fault(env, addr, is_write, mmu_idx); + ret = pcc->handle_mmu_fault(cpu, addr, is_write, mmu_idx); } else { ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx); }