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X-Received-From: 2607:f8b0:400e:c03::233 Cc: claudio.fontana@huawei.com, Richard Henderson Subject: [Qemu-devel] [PATCH v3 13/29] tcg-aarch64: Handle zero as first argument to sub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In order to properly handle neg, as generated by TCG generic code. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index eb080ed..ea1db85 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -109,6 +109,7 @@ static inline void patch_reloc(uint8_t *code_ptr, int type, #define TCG_CT_CONST_IS32 0x100 #define TCG_CT_CONST_AIMM 0x200 #define TCG_CT_CONST_LIMM 0x400 +#define TCG_CT_CONST_ZERO 0x800 /* parse target specific constraints */ static int target_parse_constraint(TCGArgConstraint *ct, @@ -142,6 +143,9 @@ static int target_parse_constraint(TCGArgConstraint *ct, case 'L': /* Valid for logical immediate. */ ct->ct |= TCG_CT_CONST_LIMM; break; + case 'Z': /* zero */ + ct->ct |= TCG_CT_CONST_ZERO; + break; default: return -1; } @@ -193,6 +197,9 @@ static int tcg_target_const_match(tcg_target_long val, if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) { return 1; } + if ((ct & TCG_CT_CONST_ZERO) && val == 0) { + return 1; + } return 0; } @@ -1166,6 +1173,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGArg a2 = args[2]; int c2 = const_args[2]; + /* Some operands are defined with "rZ" constraint, a register or + the zero register. These need not actually test args[I] == 0. */ +#define REG0(I) (const_args[I] ? TCG_REG_XZR : (TCGReg)args[I]) + switch (opc) { case INDEX_op_exit_tb: tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0); @@ -1235,9 +1246,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, /* FALLTHRU */ case INDEX_op_sub_i64: if (c2) { - tcg_out_addsubi(s, ext, a0, a1, -a2); + /* Arithmetic immediate instructions use Xn|sp, and thus + we cannot encode the zero register if tcg optimization + is turned off and both A1 and A2 are constants. */ + if (const_args[1]) { + tcg_out_movi(s, ext ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, -a2); + } else { + tcg_out_addsubi(s, ext, a0, a1, -a2); + } } else { - tcg_fmt_Rdnm(s, INSN_SUB, ext, a0, a1, a2); + tcg_fmt_Rdnm(s, INSN_SUB, ext, a0, REG0(1), a2); } break; @@ -1461,6 +1479,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, /* Opcode not implemented. */ tcg_abort(); } + +#undef REG0 } static const TCGTargetOpDef aarch64_op_defs[] = { @@ -1498,8 +1518,8 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_add_i32, { "r", "r", "rwA" } }, { INDEX_op_add_i64, { "r", "r", "rA" } }, - { INDEX_op_sub_i32, { "r", "r", "rwA" } }, - { INDEX_op_sub_i64, { "r", "r", "rA" } }, + { INDEX_op_sub_i32, { "r", "rZ", "rwA" } }, + { INDEX_op_sub_i64, { "r", "rZ", "rA" } }, { INDEX_op_mul_i32, { "r", "r", "r" } }, { INDEX_op_mul_i64, { "r", "r", "r" } }, { INDEX_op_and_i32, { "r", "r", "rwL" } },