From patchwork Mon Sep 2 03:52:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 271669 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 224D12C009E for ; Mon, 2 Sep 2013 13:53:02 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D56464A095; Mon, 2 Sep 2013 05:52:58 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id REi3M+Cet5Fp; Mon, 2 Sep 2013 05:52:58 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 58DA84A097; Mon, 2 Sep 2013 05:52:57 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A05504A097 for ; Mon, 2 Sep 2013 05:52:51 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RT0gFWiXgWq6 for ; Mon, 2 Sep 2013 05:52:46 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 086334A095 for ; Mon, 2 Sep 2013 05:52:38 +0200 (CEST) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r823qaUo012090 for ; Sun, 1 Sep 2013 22:52:37 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r823qa3S021038 for ; Sun, 1 Sep 2013 22:52:36 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.2.342.3; Sun, 1 Sep 2013 22:52:36 -0500 Received: from [172.24.145.100] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id r823qY4k005616; Sun, 1 Sep 2013 22:52:35 -0500 Message-ID: <52240B82.9090001@ti.com> Date: Mon, 2 Sep 2013 09:22:34 +0530 From: Lokesh Vutla User-Agent: Mozilla/5.0 (X11; Linux i686; rv:15.0) Gecko/20120912 Thunderbird/15.0.1 MIME-Version: 1.0 To: Tom Rini References: <1377275210-25194-1-git-send-email-trini@ti.com> <5220248E.60604@ti.com> <52210985.8080003@ti.com> <20130830211358.GW17898@bill-the-cat> In-Reply-To: <20130830211358.GW17898@bill-the-cat> Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH] am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Hi Tom, On Saturday 31 August 2013 02:43 AM, Tom Rini wrote: > On Fri, Aug 30, 2013 at 05:07:17PM -0400, Tom Rini wrote: > >> -----BEGIN PGP SIGNED MESSAGE----- >> Hash: SHA1 >> >> On 08/30/2013 12:50 AM, Sricharan R wrote: >>> Hi Tom, >>> >>> On Friday 23 August 2013 09:56 PM, Tom Rini wrote: >>>> Test on Beaglebone white over cpsw, usb ether and SD card (read and >>>> write), performance increased, crc32 of data matches. >>>> >>>> Signed-off-by: Tom Rini >>>> --- >>>> arch/arm/cpu/armv7/am33xx/board.c | 8 ++++++++ >>>> 1 file changed, 8 insertions(+) >>>> >>>> diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c >>>> index 2ea3d69..c261af5 100644 >>>> --- a/arch/arm/cpu/armv7/am33xx/board.c >>>> +++ b/arch/arm/cpu/armv7/am33xx/board.c >>>> @@ -225,3 +225,11 @@ void s_init(void) >>>> sdram_init(); >>>> #endif >>>> } >>>> + >>>> +#ifndef CONFIG_SYS_DCACHE_OFF >>>> +void enable_caches(void) >>>> +{ >>>> + /* Enable D-cache. I-cache is already enabled in start.S */ >>>> + dcache_enable(); >>>> +} >>>> +#endif /* !CONFIG_SYS_DCACHE_OFF */ >>> This is fine. Do we have secure devices here ? >>> >>> If so, we should take care of setting the domains permissions for >>> avoiding prefetch aborts. As it was done for OMAP using >>> arm_init_domains. So that function and the above should be executed on >>> am33xx as well. >>> >>> Thanks to Lokesh for reminding this. >> >> Yes, but I can't easily test them. I'll see if arm_init_domains just >> works on non-HS devices (I know I had a failure pulling all the OMAP4 >> code over, but didn't try hard, just looked again at the "easy" path). > > Yeah, that code as-is hangs the boards. So if the HS devices need > something, it'll go with the rest of their patches until we're moving it > upstream. But good to note a potential problem area! I added the following diff and I am able to boot my BBB over cpsw. AM I missing something here ? Thanks and regards, Lokesh > > > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 2ea3d69..8a1a29a 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -31,6 +31,11 @@ #include #include #include +#include + +#define ARMV7_DCACHE_WRITEBACK 0xe +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0) DECLARE_GLOBAL_DATA_PTR; @@ -225,3 +230,40 @@ void s_init(void) sdram_init(); #endif } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} + +void dram_bank_mmu_setup(int bank) +{ + bd_t *bd = gd->bd; + int i; + + u32 start = bd->bi_dram[bank].start >> 20; + u32 size = bd->bi_dram[bank].size >> 20; + u32 end = start + size; + + debug("%s: bank: %d\n", __func__, bank); + for (i = start; i < end; i++) + set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); + +} + +void arm_init_domains(void) +{ + u32 reg; + + reg = get_dacr(); + /* + * Set DOMAIN to client access so that all permissions + * set in pagetables are validated by the mmu. + */ + reg &= ~ARMV7_DOMAIN_MASK; + reg |= ARMV7_DOMAIN_CLIENT; + set_dacr(reg); +} +#endif