Patchwork [U-Boot,1/1] am33xx: add NAND cape support for beaglebone (white)

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Submitter pekon gupta
Date Aug. 30, 2013, 11:03 a.m.
Message ID <1377860613-6762-1-git-send-email-pekon@ti.com>
Download mbox | patch
Permalink /patch/271232/
State Superseded
Delegated to: Tom Rini
Headers show

Comments

pekon gupta - Aug. 30, 2013, 11:03 a.m.
beaglebone board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for using
'NAND' cape (expansion board) with Beaglebone white/
http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module

Signed-off-by: Pekon Gupta <pekon@ti.com>
---
 board/ti/am335x/mux.c | 43 +++++++++++++++++++++++++++++++++++++------
 1 file changed, 37 insertions(+), 6 deletions(-)

Patch

diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index b2bfda5..d4bd658 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -171,7 +171,35 @@  static struct module_pin_mux mii1_pin_mux[] = {
 	{-1},
 };
 
-static struct module_pin_mux nand_pin_mux[] = {
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_x16_pin_mux[] = {
+	{OFFSET(gpmc_ad0),  (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1),  (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2),  (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3),  (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4),  (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5),  (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6),  (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7),  (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_ad8),  (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD8 */
+	{OFFSET(gpmc_ad9),  (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD9 */
+	{OFFSET(gpmc_ad10), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD10 */
+	{OFFSET(gpmc_ad11), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD11 */
+	{OFFSET(gpmc_ad12), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD12 */
+	{OFFSET(gpmc_ad13), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD13 */
+	{OFFSET(gpmc_ad14), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD14 */
+	{OFFSET(gpmc_ad15), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD15 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+static struct module_pin_mux nand_x8_pin_mux[] = {
 	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
 	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
 	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
@@ -189,7 +217,7 @@  static struct module_pin_mux nand_pin_mux[] = {
 	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
 	{-1},
 };
-
+#endif
 #if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
 static struct module_pin_mux bone_norcape_pin_mux[] = {
 	{OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A0 */
@@ -336,11 +364,12 @@  void enable_board_pin_mux(struct am335x_baseboard_id *header)
 		configure_module_pin_mux(i2c1_pin_mux);
 		configure_module_pin_mux(mii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
-#ifndef CONFIG_NOR
-		configure_module_pin_mux(mmc1_pin_mux);
-#endif
 #if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
 		configure_module_pin_mux(bone_norcape_pin_mux);
+#elif defined(CONFIG_NAND)
+		configure_module_pin_mux(nand_x16_pin_mux);
+#else
+		configure_module_pin_mux(mmc1_pin_mux);
 #endif
 	} else if (board_is_gp_evm(header)) {
 		/* General Purpose EVM */
@@ -351,8 +380,10 @@  void enable_board_pin_mux(struct am335x_baseboard_id *header)
 		if (profile & ~PROFILE_2)
 			configure_module_pin_mux(i2c1_pin_mux);
 		/* Profiles 2 & 3 don't have NAND */
+#ifdef CONFIG_NAND
 		if (profile & ~(PROFILE_2 | PROFILE_3))
-			configure_module_pin_mux(nand_pin_mux);
+			configure_module_pin_mux(nand_x8_pin_mux);
+#endif
 		else if (profile == PROFILE_2) {
 			configure_module_pin_mux(mmc1_pin_mux);
 			configure_module_pin_mux(spi0_pin_mux);