Patchwork [v2,5/6] ARM: tegra: Add host1x, DC and HDMI to Tegra114 device tree

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Submitter Mikko Perttunen
Date Aug. 28, 2013, 3:48 p.m.
Message ID <1377704922-2824-6-git-send-email-mperttunen@nvidia.com>
Download mbox | patch
Permalink /patch/270579/
State Superseded, archived
Headers show

Comments

Mikko Perttunen - Aug. 28, 2013, 3:48 p.m.
Add host1x, DC (display controller) and HDMI devices to Tegra114
device tree.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi | 42 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
Stephen Warren - Sept. 4, 2013, 6:46 p.m.
On 08/28/2013 09:48 AM, Mikko Perttunen wrote:
> Add host1x, DC (display controller) and HDMI devices to Tegra114
> device tree.

Patches 5 and 6 should be sent separately to the Tegra maintainer (me)
to be taken through the Tegra tree.
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Patch

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 2905145..088b594 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -27,6 +27,48 @@ 
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
+	host1x {
+		compatible = "nvidia,tegra114-host1x", "simple-bus";
+		reg = <0x50000000 0x00028000>;
+		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ranges = <0x54000000 0x54000000 0x04000000>;
+
+		dc@54200000 {
+			compatible = "nvidia,tegra114-dc", "nvidia,tegra30-dc";
+			reg = <0x54200000 0x00040000>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&tegra_car TEGRA114_CLK_DISP1>,
+				    <&tegra_car TEGRA114_CLK_PLL_P>;
+			clock-names = "disp1", "parent";
+		};
+
+		dc@54240000 {
+			compatible = "nvidia,tegra114-dc", "nvidia,tegra30-dc";
+			reg = <0x54240000 0x00040000>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&tegra_car TEGRA114_CLK_DISP2>,
+				    <&tegra_car TEGRA114_CLK_PLL_P>;
+			clock-names = "disp2", "parent";
+		};
+
+		hdmi {
+			compatible = "nvidia,tegra114-hdmi";
+			reg = <0x54280000 0x00040000>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&tegra_car TEGRA114_CLK_HDMI>,
+				    <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
+			clock-names = "hdmi", "parent";
+
+			status = "disabled";
+		};
+	};
+
 	timer@60005000 {
 		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
 		reg = <0x60005000 0x400>;