From patchwork Wed Aug 28 14:04:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Longchamp X-Patchwork-Id: 270522 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DBBC82C009A for ; Thu, 29 Aug 2013 00:07:33 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D0BCC4A088; Wed, 28 Aug 2013 16:07:31 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vi87Te2BhlmU; Wed, 28 Aug 2013 16:07:31 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3A0C64A087; Wed, 28 Aug 2013 16:07:23 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 91AFC4A066 for ; Wed, 28 Aug 2013 16:07:20 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nkxxu8r+T3FH for ; Wed, 28 Aug 2013 16:07:15 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-de.keymile.com (mail-de.keymile.com [195.8.104.250]) by theia.denx.de (Postfix) with ESMTPS id 43AF24A065 for ; Wed, 28 Aug 2013 16:07:10 +0200 (CEST) Received: from [10.9.1.54] (port=62623 helo=mailrelay.de.keymile.net) by mail-de.keymile.com with esmtp (Exim 4.76) (envelope-from ) id 1VEgMN-0004Yi-2p; Wed, 28 Aug 2013 16:04:35 +0200 Received: from chber1-10533x.keymile.net (chber1-10533x.keymile.net [172.31.40.3]) by mailrelay.de.keymile.net (8.12.2/8.12.2) with ESMTP id r7SE2F1c016377; Wed, 28 Aug 2013 16:02:19 +0200 (MEST) From: Valentin Longchamp To: Andy Fleming , Scott Wood , York Sun Date: Wed, 28 Aug 2013 16:04:24 +0200 Message-Id: <1377698669-6149-7-git-send-email-valentin.longchamp@keymile.com> X-Mailer: git-send-email 1.8.0.1 In-Reply-To: <1377698669-6149-1-git-send-email-valentin.longchamp@keymile.com> References: <1377698669-6149-1-git-send-email-valentin.longchamp@keymile.com> Cc: U-Boot Mailing List , Holger Brunck , Valentin Longchamp Subject: [U-Boot] [PATCH v2 06/11] mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de If the DDR3 module supports industrial temperature range and requires the x2 refresh rate for that temp range, the refresh period must be 3.9us instead of 7.8 us. Signed-off-by: Valentin Longchamp --- Changes in v2: - when refresh rate gets halved for extended range temperature operations, the srt bit in the mode register 2 is set. arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h | 1 + arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 7 ++++++- arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 4 ++++ arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 5 +++++ arch/powerpc/include/asm/fsl_ddr_dimm_params.h | 1 + 5 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h index 06706ed..48de019 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h @@ -28,6 +28,7 @@ typedef struct { unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ unsigned int refresh_rate_ps; + unsigned int extended_op_srt; unsigned int tIS_ps; /* byte 32, spd->ca_setup */ unsigned int tIH_ps; /* byte 33, spd->ca_hold */ diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 26c42f7..108e4d6 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -764,6 +764,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, + const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) { unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ @@ -781,6 +782,10 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, rtt_wr = popts->rtt_wr_override_value; else rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; + + if (common_dimm->extended_op_srt) + srt = common_dimm->extended_op_srt; + esdmode2 = (0 | ((rtt_wr & 0x3) << 9) | ((srt & 0x1) << 7) @@ -1625,7 +1630,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en); set_ddr_sdram_mode(ddr, popts, common_dimm, cas_latency, additive_latency, unq_mrs_en); - set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en); + set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en); set_ddr_sdram_interval(ddr, popts, common_dimm); set_ddr_data_init(ddr); set_ddr_sdram_clk_cntl(ddr, popts); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index 3e7c269..7e4dfd1 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -320,6 +320,10 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * = 3.9 us at ext temperature range */ pdimm->refresh_rate_ps = 7800000; + if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) { + pdimm->refresh_rate_ps = 3900000; + pdimm->extended_op_srt = 1; + } /* * min four active window delay time diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index e958e13..d5e09e5 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -92,6 +92,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, unsigned int tRRD_ps = 0; unsigned int tRC_ps = 0; unsigned int refresh_rate_ps = 0; + unsigned int extended_op_srt = 1; unsigned int tIS_ps = 0; unsigned int tIH_ps = 0; unsigned int tDS_ps = 0; @@ -166,6 +167,9 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps); refresh_rate_ps = max(refresh_rate_ps, dimm_params[i].refresh_rate_ps); + /* extended_op_srt is either 0 or 1, 0 having priority */ + extended_op_srt = min(extended_op_srt, + dimm_params[i].extended_op_srt); /* * Find maximum tDQSQ_max_ps to find slowest. @@ -195,6 +199,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, outpdimm->tRRD_ps = tRRD_ps; outpdimm->tRC_ps = tRC_ps; outpdimm->refresh_rate_ps = refresh_rate_ps; + outpdimm->extended_op_srt = extended_op_srt; outpdimm->tIS_ps = tIS_ps; outpdimm->tIH_ps = tIH_ps; outpdimm->tDS_ps = tDS_ps; diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h index ffe4db8..6c8376f 100644 --- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h +++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h @@ -77,6 +77,7 @@ typedef struct dimm_params_s { unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ unsigned int refresh_rate_ps; + unsigned int extended_op_srt; /* DDR3 doesn't need these as below */ unsigned int tIS_ps; /* byte 32, spd->ca_setup */