Patchwork [U-Boot,v2,06/11] mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it

login
register
mail settings
Submitter Valentin Longchamp
Date Aug. 28, 2013, 2:04 p.m.
Message ID <1377698669-6149-7-git-send-email-valentin.longchamp@keymile.com>
Download mbox | patch
Permalink /patch/270522/
State Superseded
Delegated to: York Sun
Headers show

Comments

Valentin Longchamp - Aug. 28, 2013, 2:04 p.m.
If the DDR3 module supports industrial temperature range and requires
the x2 refresh rate for that temp range, the refresh period must be
3.9us instead of 7.8 us.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

---
Changes in v2:
- when refresh rate gets halved for extended range temperature
  operations, the srt bit in the mode register 2 is set.

 arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h  | 1 +
 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c             | 7 ++++++-
 arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c      | 4 ++++
 arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 5 +++++
 arch/powerpc/include/asm/fsl_ddr_dimm_params.h       | 1 +
 5 files changed, 17 insertions(+), 1 deletion(-)
York Sun - Sept. 6, 2013, 8:05 p.m.
On 08/28/2013 07:04 AM, Valentin Longchamp wrote:
> If the DDR3 module supports industrial temperature range and requires
> the x2 refresh rate for that temp range, the refresh period must be
> 3.9us instead of 7.8 us.
> 
> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
> 
> ---
> 

Can you add a line in commit message about on which board, what model
memory modules have been verified?

York

Patch

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
index 06706ed..48de019 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
@@ -28,6 +28,7 @@  typedef struct {
 	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
 
 	unsigned int refresh_rate_ps;
+	unsigned int extended_op_srt;
 
 	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
 	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 26c42f7..108e4d6 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -764,6 +764,7 @@  static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
+				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
 {
 	unsigned short esdmode2 = 0;	/* Extended SDRAM mode 2 */
@@ -781,6 +782,10 @@  static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 		rtt_wr = popts->rtt_wr_override_value;
 	else
 		rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
+
+	if (common_dimm->extended_op_srt)
+		srt = common_dimm->extended_op_srt;
+
 	esdmode2 = (0
 		| ((rtt_wr & 0x3) << 9)
 		| ((srt & 0x1) << 7)
@@ -1625,7 +1630,7 @@  compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
 	set_ddr_sdram_mode(ddr, popts, common_dimm,
 				cas_latency, additive_latency, unq_mrs_en);
-	set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
+	set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
 	set_ddr_sdram_interval(ddr, popts, common_dimm);
 	set_ddr_data_init(ddr);
 	set_ddr_sdram_clk_cntl(ddr, popts);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index 3e7c269..7e4dfd1 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -320,6 +320,10 @@  ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
 	 *       = 3.9 us at ext temperature range
 	 */
 	pdimm->refresh_rate_ps = 7800000;
+	if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) {
+		pdimm->refresh_rate_ps = 3900000;
+		pdimm->extended_op_srt = 1;
+	}
 
 	/*
 	 * min four active window delay time
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index e958e13..d5e09e5 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -92,6 +92,7 @@  compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	unsigned int tRRD_ps = 0;
 	unsigned int tRC_ps = 0;
 	unsigned int refresh_rate_ps = 0;
+	unsigned int extended_op_srt = 1;
 	unsigned int tIS_ps = 0;
 	unsigned int tIH_ps = 0;
 	unsigned int tDS_ps = 0;
@@ -166,6 +167,9 @@  compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 		tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps);
 		refresh_rate_ps = max(refresh_rate_ps,
 				      dimm_params[i].refresh_rate_ps);
+		/* extended_op_srt is either 0 or 1, 0 having priority */
+		extended_op_srt = min(extended_op_srt,
+				      dimm_params[i].extended_op_srt);
 
 		/*
 		 * Find maximum tDQSQ_max_ps to find slowest.
@@ -195,6 +199,7 @@  compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	outpdimm->tRRD_ps = tRRD_ps;
 	outpdimm->tRC_ps = tRC_ps;
 	outpdimm->refresh_rate_ps = refresh_rate_ps;
+	outpdimm->extended_op_srt = extended_op_srt;
 	outpdimm->tIS_ps = tIS_ps;
 	outpdimm->tIH_ps = tIH_ps;
 	outpdimm->tDS_ps = tDS_ps;
diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
index ffe4db8..6c8376f 100644
--- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
+++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
@@ -77,6 +77,7 @@  typedef struct dimm_params_s {
 	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
 
 	unsigned int refresh_rate_ps;
+	unsigned int extended_op_srt;
 
 	/* DDR3 doesn't need these as below */
 	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */