From patchwork Wed Aug 28 14:04:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Longchamp X-Patchwork-Id: 270519 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 516862C009A for ; Thu, 29 Aug 2013 00:06:12 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F00C84A0D5; Wed, 28 Aug 2013 16:05:57 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id h6J6I2pnzpfD; Wed, 28 Aug 2013 16:05:57 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8678E4A09E; Wed, 28 Aug 2013 16:05:12 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 322584A08D for ; Wed, 28 Aug 2013 16:04:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RMZjPzc1GycQ for ; Wed, 28 Aug 2013 16:04:48 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-de.keymile.com (mail-de.keymile.com [195.8.104.250]) by theia.denx.de (Postfix) with ESMTPS id 4395C4A07F for ; Wed, 28 Aug 2013 16:04:39 +0200 (CEST) Received: from [10.9.1.54] (port=62629 helo=mailrelay.de.keymile.net) by mail-de.keymile.com with esmtp (Exim 4.76) (envelope-from ) id 1VEgMP-0004ZS-1P; Wed, 28 Aug 2013 16:04:37 +0200 Received: from chber1-10533x.keymile.net (chber1-10533x.keymile.net [172.31.40.3]) by mailrelay.de.keymile.net (8.12.2/8.12.2) with ESMTP id r7SE2F1f016377; Wed, 28 Aug 2013 16:02:20 +0200 (MEST) From: Valentin Longchamp To: Andy Fleming , Scott Wood , York Sun Date: Wed, 28 Aug 2013 16:04:27 +0200 Message-Id: <1377698669-6149-10-git-send-email-valentin.longchamp@keymile.com> X-Mailer: git-send-email 1.8.0.1 In-Reply-To: <1377698669-6149-1-git-send-email-valentin.longchamp@keymile.com> References: <1377698669-6149-1-git-send-email-valentin.longchamp@keymile.com> Cc: U-Boot Mailing List , Holger Brunck , Valentin Longchamp Subject: [U-Boot] [PATCH v2 09/11] fsl/mpc85xx: introduce fsl_print_rcw function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The RCW gets printed on a lot of FSL 85xx devices and it is always done the same way. The fsl_print_rcw function performs this exact same task. Signed-off-by: Valentin Longchamp --- Changes in v2: None arch/powerpc/cpu/mpc85xx/Makefile | 1 + arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c | 43 ++++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_rcw.h | 19 +++++++++++++ board/freescale/b4860qds/b4860qds.c | 13 ++------- board/freescale/corenet_ds/corenet_ds.c | 24 +++++++---------- board/freescale/t4qds/t4qds.c | 12 ++------- 6 files changed, 76 insertions(+), 36 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c create mode 100644 arch/powerpc/include/asm/fsl_rcw.h diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 4669883..8c51619 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -114,6 +114,7 @@ COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o +COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_rcw.o # SoC specific SERDES support COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c new file mode 100644 index 0000000..ca3a566 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_rcw.c @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include + +#ifdef CONFIG_FSL_CORENET +void fsl_print_rcw(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + unsigned int i; + + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); +} +#endif + diff --git a/arch/powerpc/include/asm/fsl_rcw.h b/arch/powerpc/include/asm/fsl_rcw.h new file mode 100644 index 0000000..077f176 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_rcw.h @@ -0,0 +1,19 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __ASM_PPC_FSL_RCW_H +#define __ASM_PPC_FSL_RCW_H + +void fsl_print_rcw(void); + +#endif /* __ASM_PPC_FSL_RCW_H */ diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index a39c17a..e9817c0 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include "../common/qixis.h" @@ -51,8 +52,6 @@ int checkboard(void) char buf[64]; u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - unsigned int i; static const char *const freq[] = {"100", "125", "156.25", "161.13", "122.88", "122.88", "122.88"}; int clock; @@ -80,15 +79,7 @@ int checkboard(void) /* Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); + fsl_print_rcw(); /* * Display the actual SERDES reference clocks as configured by the diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 48f7155..33e2aa5 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include "../common/ngpixis.h" @@ -43,8 +44,6 @@ int checkboard (void) { u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - unsigned int i; static const char * const freq[] = {"100", "125", "156.25", "212.5" }; printf("Board: %sDS, ", cpu->name); @@ -66,15 +65,7 @@ int checkboard (void) /* Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); + fsl_print_rcw(); /* Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could @@ -86,11 +77,14 @@ int checkboard (void) puts("SERDES Reference Clocks: "); #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ || defined(CONFIG_P5040DS) - sw = in_8(&PIXIS_SW(5)); - for (i = 0; i < 3; i++) { - unsigned int clock = (sw >> (6 - (2 * i))) & 3; + { + unsigned int i; + sw = in_8(&PIXIS_SW(5)); + for (i = 0; i < 3; i++) { + unsigned int clock = (sw >> (6 - (2 * i))) & 3; - printf("Bank%u=%sMhz ", i+1, freq[clock]); + printf("Bank%u=%sMhz ", i+1, freq[clock]); + } } #ifdef CONFIG_P5040DS /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c index f0f280b..3ec1509 100644 --- a/board/freescale/t4qds/t4qds.c +++ b/board/freescale/t4qds/t4qds.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include "../common/qixis.h" @@ -59,7 +60,6 @@ int checkboard(void) char buf[64]; u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; unsigned int i; printf("Board: %sQDS, ", cpu->name); @@ -87,15 +87,7 @@ int checkboard(void) /* Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); + fsl_print_rcw(); /* * Display the actual SERDES reference clocks as configured by the