From patchwork Tue Aug 27 08:41:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dongsheng Wang X-Patchwork-Id: 270068 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 5FC332C0455 for ; Tue, 27 Aug 2013 18:45:39 +1000 (EST) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe004.messaging.microsoft.com [216.32.181.184]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "MSIT Machine Auth CA 2" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 2A8532C0133 for ; Tue, 27 Aug 2013 18:44:12 +1000 (EST) Received: from mail134-ch1-R.bigfish.com (10.43.68.227) by CH1EHSOBE002.bigfish.com (10.43.70.52) with Microsoft SMTP Server id 14.1.225.22; Tue, 27 Aug 2013 08:44:07 +0000 Received: from mail134-ch1 (localhost [127.0.0.1]) by mail134-ch1-R.bigfish.com (Postfix) with ESMTP id BC0C824021F; Tue, 27 Aug 2013 08:44:07 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h1155h) Received: from mail134-ch1 (localhost.localdomain [127.0.0.1]) by mail134-ch1 (MessageSwitch) id 1377593045416918_497; Tue, 27 Aug 2013 08:44:05 +0000 (UTC) Received: from CH1EHSMHS014.bigfish.com (snatpool2.int.messaging.microsoft.com [10.43.68.233]) by mail134-ch1.bigfish.com (Postfix) with ESMTP id 57C714A0041; Tue, 27 Aug 2013 08:44:05 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS014.bigfish.com (10.43.70.14) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 27 Aug 2013 08:44:05 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.3.146.2; Tue, 27 Aug 2013 08:44:04 +0000 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r7R8hpKR022069; Tue, 27 Aug 2013 01:44:02 -0700 From: Dongsheng Wang To: , Subject: [PATCH v2 3/3] powerpc/85xx: add hardware automatically enter pw20 state Date: Tue, 27 Aug 2013 16:41:40 +0800 Message-ID: <1377592900-5020-3-git-send-email-dongsheng.wang@freescale.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1377592900-5020-1-git-send-email-dongsheng.wang@freescale.com> References: <1377592900-5020-1-git-send-email-dongsheng.wang@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: linuxppc-dev@lists.ozlabs.org, Wang Dongsheng X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.16rc2 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Wang Dongsheng Using hardware features make core automatically enter PW20 state. Set a TB count to hardware, the effective count begins when PW10 is entered. When the effective period has expired, the core will proceed from PW10 to PW20 if no exit conditions have occurred during the period. Signed-off-by: Wang Dongsheng --- Remove: delete setup_idle_hw_governor function. delete "Fix erratum" for rev1. Move: move setup_* into __setup/restore_cpu_e6500. diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 8364bbe..e846495 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -219,6 +219,7 @@ /* Bit definitions for PWRMGTCR0. */ #define PWRMGTCR0_ALTIVEC_IDLE (1 << 22) /* Altivec idle enable */ +#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */ /* Bit definitions for the MCSR. */ #define MCSR_MCS 0x80000000 /* Machine Check Summary */ diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 90bbb46..295ccb5 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -59,6 +59,7 @@ _GLOBAL(__setup_cpu_e6500) bl .setup_altivec_ivors #endif bl setup_altivec_idle + bl setup_pw20_idle bl __setup_cpu_e5500 mtlr r6 blr @@ -121,6 +122,7 @@ _GLOBAL(__restore_cpu_e6500) mflr r5 bl .setup_altivec_ivors bl setup_altivec_idle + bl setup_pw20_idle bl __restore_cpu_e5500 mtlr r5 blr diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c index 93b563b..cdd526e 100644 --- a/arch/powerpc/platforms/85xx/common.c +++ b/arch/powerpc/platforms/85xx/common.c @@ -15,12 +15,22 @@ #define ALTIVEC_COUNT_OFFSET 16 #define ALTIVEC_IDLE_COUNT_MASK 0x003f0000 +#define PW20_COUNT_OFFSET 8 +#define PW20_IDLE_COUNT_MASK 0x00003f00 /* * FIXME - We don't know the AltiVec application scenarios. */ #define ALTIVEC_IDLE_TIME_BIT 14 /* 1ms */ +/* + * FIXME - We don't know, what time should we let the core into PW20 state. + * because we don't know the current state of the cpu load. And threads are + * independent, so we can not know the state of different thread has been + * idle. + */ +#define PW20_IDLE_TIME_BIT 14 /* 1ms */ + static struct of_device_id __initdata mpc85xx_common_ids[] = { { .type = "soc", }, { .compatible = "soc", }, @@ -125,3 +135,25 @@ void setup_altivec_idle(void) mtspr(SPRN_PWRMGTCR0, altivec_idle); } + +void setup_pw20_idle(void) +{ + u32 pw20_idle; + + if (!has_pw20_altivec_idle()) + return; + + pw20_idle = mfspr(SPRN_PWRMGTCR0); + + /* Set PW20_WAIT bit, Enable PW20 State */ + pw20_idle |= PWRMGTCR0_PW20_WAIT; + + /* Set Automatic PW20 Core Idle Count */ + /* clear count */ + pw20_idle &= ~PW20_IDLE_COUNT_MASK; + + /* set count */ + pw20_idle |= ((MAX_BIT - PW20_IDLE_TIME_BIT) << PW20_COUNT_OFFSET); + + mtspr(SPRN_PWRMGTCR0, pw20_idle); +}