Patchwork [U-Boot] am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF

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Submitter Tom Rini
Date Aug. 23, 2013, 4:26 p.m.
Message ID <1377275210-25194-1-git-send-email-trini@ti.com>
Download mbox | patch
Permalink /patch/269494/
State Accepted
Delegated to: Tom Rini
Headers show

Comments

Tom Rini - Aug. 23, 2013, 4:26 p.m.
Test on Beaglebone white over cpsw, usb ether and SD card (read and
write), performance increased, crc32 of data matches.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/board.c |    8 ++++++++
 1 file changed, 8 insertions(+)
SRICHARAN R - Aug. 30, 2013, 4:50 a.m.
Hi Tom,

On Friday 23 August 2013 09:56 PM, Tom Rini wrote:
> Test on Beaglebone white over cpsw, usb ether and SD card (read and
> write), performance increased, crc32 of data matches.
>
> Signed-off-by: Tom Rini <trini@ti.com>
> ---
>  arch/arm/cpu/armv7/am33xx/board.c |    8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
> index 2ea3d69..c261af5 100644
> --- a/arch/arm/cpu/armv7/am33xx/board.c
> +++ b/arch/arm/cpu/armv7/am33xx/board.c
> @@ -225,3 +225,11 @@ void s_init(void)
>  	sdram_init();
>  #endif
>  }
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +void enable_caches(void)
> +{
> +	/* Enable D-cache. I-cache is already enabled in start.S */
> +	dcache_enable();
> +}
> +#endif /* !CONFIG_SYS_DCACHE_OFF */
 This is fine. Do we have secure devices here ?

 If so, we should take care of setting the domains permissions for
 avoiding prefetch aborts. As it was done for OMAP using
 arm_init_domains. So that function and the above should be executed on
 am33xx as well.

 Thanks to Lokesh for reminding this.

Regards,
 Sricharan
Tom Rini - Aug. 30, 2013, 9:07 p.m.
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 08/30/2013 12:50 AM, Sricharan R wrote:
> Hi Tom,
> 
> On Friday 23 August 2013 09:56 PM, Tom Rini wrote:
>> Test on Beaglebone white over cpsw, usb ether and SD card (read and
>> write), performance increased, crc32 of data matches.
>>
>> Signed-off-by: Tom Rini <trini@ti.com>
>> ---
>>  arch/arm/cpu/armv7/am33xx/board.c |    8 ++++++++
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
>> index 2ea3d69..c261af5 100644
>> --- a/arch/arm/cpu/armv7/am33xx/board.c
>> +++ b/arch/arm/cpu/armv7/am33xx/board.c
>> @@ -225,3 +225,11 @@ void s_init(void)
>>  	sdram_init();
>>  #endif
>>  }
>> +
>> +#ifndef CONFIG_SYS_DCACHE_OFF
>> +void enable_caches(void)
>> +{
>> +	/* Enable D-cache. I-cache is already enabled in start.S */
>> +	dcache_enable();
>> +}
>> +#endif /* !CONFIG_SYS_DCACHE_OFF */
>  This is fine. Do we have secure devices here ?
> 
>  If so, we should take care of setting the domains permissions for
>  avoiding prefetch aborts. As it was done for OMAP using
>  arm_init_domains. So that function and the above should be executed on
>  am33xx as well.
> 
>  Thanks to Lokesh for reminding this.

Yes, but I can't easily test them.  I'll see if arm_init_domains just
works on non-HS devices (I know I had a failure pulling all the OMAP4
code over, but didn't try hard, just looked again at the "easy" path).

- -- 
Tom
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Tom Rini - Aug. 30, 2013, 9:13 p.m.
On Fri, Aug 30, 2013 at 05:07:17PM -0400, Tom Rini wrote:

> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> On 08/30/2013 12:50 AM, Sricharan R wrote:
> > Hi Tom,
> > 
> > On Friday 23 August 2013 09:56 PM, Tom Rini wrote:
> >> Test on Beaglebone white over cpsw, usb ether and SD card (read and
> >> write), performance increased, crc32 of data matches.
> >>
> >> Signed-off-by: Tom Rini <trini@ti.com>
> >> ---
> >>  arch/arm/cpu/armv7/am33xx/board.c |    8 ++++++++
> >>  1 file changed, 8 insertions(+)
> >>
> >> diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
> >> index 2ea3d69..c261af5 100644
> >> --- a/arch/arm/cpu/armv7/am33xx/board.c
> >> +++ b/arch/arm/cpu/armv7/am33xx/board.c
> >> @@ -225,3 +225,11 @@ void s_init(void)
> >>  	sdram_init();
> >>  #endif
> >>  }
> >> +
> >> +#ifndef CONFIG_SYS_DCACHE_OFF
> >> +void enable_caches(void)
> >> +{
> >> +	/* Enable D-cache. I-cache is already enabled in start.S */
> >> +	dcache_enable();
> >> +}
> >> +#endif /* !CONFIG_SYS_DCACHE_OFF */
> >  This is fine. Do we have secure devices here ?
> > 
> >  If so, we should take care of setting the domains permissions for
> >  avoiding prefetch aborts. As it was done for OMAP using
> >  arm_init_domains. So that function and the above should be executed on
> >  am33xx as well.
> > 
> >  Thanks to Lokesh for reminding this.
> 
> Yes, but I can't easily test them.  I'll see if arm_init_domains just
> works on non-HS devices (I know I had a failure pulling all the OMAP4
> code over, but didn't try hard, just looked again at the "easy" path).

Yeah, that code as-is hangs the boards.  So if the HS devices need
something, it'll go with the rest of their patches until we're moving it
upstream.  But good to note a potential problem area!
Tom Rini - Dec. 13, 2013, 12:46 p.m.
On Fri, Aug 23, 2013 at 12:26:49PM -0400, Tom Rini wrote:

> Test on Beaglebone white over cpsw, usb ether and SD card (read and
> write), performance increased, crc32 of data matches.
> 
> Signed-off-by: Tom Rini <trini@ti.com>

Applied to u-boot-ti/master, thanks!

Patch

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 2ea3d69..c261af5 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -225,3 +225,11 @@  void s_init(void)
 	sdram_init();
 #endif
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif /* !CONFIG_SYS_DCACHE_OFF */