Patchwork [U-Boot,4/4] net: sh-eth: Add support R8A7790

login
register
mail settings
Submitter Nobuhiro Iwamatsu
Date Aug. 22, 2013, 4:22 a.m.
Message ID <1377145324-30015-4-git-send-email-nobuhiro.iwamatsu.yj@renesas.com>
Download mbox | patch
Permalink /patch/268949/
State Accepted
Delegated to: Joe Hershberger
Headers show

Comments

Nobuhiro Iwamatsu - Aug. 22, 2013, 4:22 a.m.
R8A7790 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7790.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
---
 drivers/net/sh_eth.c | 5 ++++-
 drivers/net/sh_eth.h | 7 +++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

Patch

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index b7dc625..b936808 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -4,6 +4,7 @@ 
  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
  * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
+ * Copyright (C) 2013  Renesas Electronics Corporation
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -409,6 +410,8 @@  static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 
 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 	sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
+#elif defined(CONFIG_R8A7790)
+	sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
 #endif
 	/* Configure phy */
 	ret = sh_eth_phy_config(eth);
@@ -432,7 +435,7 @@  static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 		sh_eth_write(eth, GECMR_100B, GECMR);
 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 		sh_eth_write(eth, 1, RTRATE);
-#elif defined(CONFIG_CPU_SH7724)
+#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790)
 		val = ECMR_RTM;
 #endif
 	} else if (phy->speed == 10) {
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 35a1eee..43b8ac9 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -166,6 +166,7 @@  enum {
 	TLFRCR,
 	CERCR,
 	CEECR,
+	RMIIMR, /* R8A7790 */
 	MAFCR,
 	RTRATE,
 	CSMR,
@@ -272,6 +273,7 @@  static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 	[RMCR]	= 0x0058,
 	[TFUCR]	= 0x0064,
 	[RFOCR]	= 0x0068,
+	[RMIIMR] = 0x006C,
 	[FCFTR]	= 0x0070,
 	[RPADIR]	= 0x0078,
 	[TRIMD]	= 0x007c,
@@ -299,6 +301,9 @@  static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #elif defined(CONFIG_R8A7740)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR	0xE9A00000
+#elif defined(CONFIG_R8A7790)
+#define SH_ETH_TYPE_ETHER
+#define BASE_IO_ADDR	0xEE700200
 #endif
 
 /*
@@ -502,6 +507,8 @@  enum FELIC_MODE_BIT {
 	ECMR_PRM = 0x00000001,
 #ifdef CONFIG_CPU_SH7724
 	ECMR_RTM = 0x00000010,
+#elif defined(CONFIG_R8A7790)
+	ECMR_RTM = 0x00000004,
 #endif
 
 };