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[U-Boot,v2,6/7] config: arm: exynos5250: Define CONFIG_SYS_CACHELINE_SIZE

Message ID 1377079968-1077-7-git-send-email-gautam.vivek@samsung.com
State Superseded
Delegated to: Marek Vasut
Headers show

Commit Message

Vivek Gautam Aug. 21, 2013, 10:12 a.m. UTC 
XHCI stack driver needs this to align buffers to
CacheLine boundary. So define the same to be '64'

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>
---
 include/configs/exynos5250-dt.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

Comments

Marek Vasut Sept. 4, 2013, 2:13 p.m. UTC | #1 
Dear Vivek Gautam,

> XHCI stack driver needs this to align buffers to
> CacheLine boundary. So define the same to be '64'
> 
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> Cc: Julius Werner <jwerner@chromium.org>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Minkyu Kang <mk7.kang@samsung.com>
> Cc: Dan Murphy <dmurphy@ti.com>
> Cc: Marek Vasut <marex@denx.de>
> ---
>  include/configs/exynos5250-dt.h |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/include/configs/exynos5250-dt.h
> b/include/configs/exynos5250-dt.h index 8f8f85f..86d57e3 100644
> --- a/include/configs/exynos5250-dt.h
> +++ b/include/configs/exynos5250-dt.h
> @@ -37,6 +37,8 @@
>  /* Keep L2 Cache Disabled */
>  #define CONFIG_SYS_DCACHE_OFF
> 
> +#define CONFIG_SYS_CACHELINE_SIZE	64
> +
>  /* Enable ACE acceleration for SHA1 and SHA256 */
>  #define CONFIG_EXYNOS_ACE_SHA
>  #define CONFIG_SHA_HW_ACCEL

Albert, care to apply this one separatelly?

Best regards,
Marek Vasut
diff mbox

Patch

diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 8f8f85f..86d57e3 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -37,6 +37,8 @@ 
 /* Keep L2 Cache Disabled */
 #define CONFIG_SYS_DCACHE_OFF
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /* Enable ACE acceleration for SHA1 and SHA256 */
 #define CONFIG_EXYNOS_ACE_SHA
 #define CONFIG_SHA_HW_ACCEL