From patchwork Tue Aug 20 15:04:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Praveen X-Patchwork-Id: 268576 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 3403B2C010F for ; Wed, 21 Aug 2013 01:05:47 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :in-reply-to:content-type; q=dns; s=default; b=sZ63gJUXuaQUzhbwx MbHC0+LMPGs7pK+eepPUfCLZBxrDDTXLyBtaIQHTfAePzG66/0llU7HFtt6G2kOS H7lEhx443p3aULB4p87LXgPOSguqb5eaVtK7XX7loR7pBAsehyR2xdoFIpV1Q0WS 9hxbpkeh/V2KgDPNQl7br6zgxY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :in-reply-to:content-type; s=default; bh=PtOFYM5F4v4vK/tZOg+ifyr oz/8=; b=YT+YTO/JMUWYige/98GhEy8o8grRU8k9aAew8m3iH3VFifOfVnx5+a7 w3DV813szMOu6MekdtzO5phEGiqRP2gpOpCTboNQi2wZSK/rVzVCAmLHr6CnRZLF WZVBXpJ+T1hk1MHk3z015DDAljacXlqncw4/D3Qf9EbPkUb2Jk1s= Received: (qmail 19868 invoked by alias); 20 Aug 2013 15:04:33 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 19755 invoked by uid 89); 20 Aug 2013 15:04:32 -0000 X-Spam-SWARE-Status: No, score=-4.8 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_W, RCVD_IN_HOSTKARMA_WL, SPF_PASS autolearn=ham version=3.3.2 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Tue, 20 Aug 2013 15:04:31 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 20 Aug 2013 16:04:27 +0100 Received: from e103625-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Tue, 20 Aug 2013 16:04:27 +0100 Date: Tue, 20 Aug 2013 16:04:26 +0100 From: Vidya Praveen To: "gcc-patches@gcc.gnu.org" Cc: Marcus Shawcroft Subject: Re: [Patch,AArch64] Support SISD Shifts (SHL/USHR/SSHL/USHL/SSHR) Message-ID: <20130820150426.GC21223@e103625-lin.cambridge.arm.com> References: <20130820150159.GB21223@e103625-lin.cambridge.arm.com> MIME-Version: 1.0 In-Reply-To: <20130820150159.GB21223@e103625-lin.cambridge.arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-MC-Unique: 113082016042702701 Content-Disposition: inline X-Virus-Found: No With the attachment this time :-) Regards VP On Tue, Aug 20, 2013 at 04:01:59PM +0100, Vidya Praveen wrote: > Hello, > > This patch supports SISD shift instructions SHL/USHR/SSHR/SSHL/USHL for > SImode and DImode. This patch also refactors the integer shifts pattern > "3_insn". Pattern for rotate is moved out as ror3_insn. > > Shift patterns (aarch64_{lshr|ashl|ashr}_sisd_or_int_{si|di}3) support > both SIMD registers and general purpose registers with the shift quantity > either as variable or literal. Since there are no SISD instructions for > right shifts, the instruction SSHL and USHL are used with shift operand > negated using NEG in order reverse the direction. This is done by > insisting on splitting (after reload) in to neg and UNSPEC_SISD_USHL or > UNSPEC_SISD_SSHL or UNSPEC_USHL_S2 or UNSPEC_SSHL_S2 pattern. Since there > are no SISD variants of shift instructions available for SImode, the SIMD > variants of corresponsing instructions are used with 2S size by taking > one lane alone in to cosideration and ignoring other. > > This patch also introduces a predicate aarch64_simd_register to help in > splitting patterns. Tests for both newly introduced instructions as well > as for the integer instructions are included. > > Tested and no new regressions. > > OK for trunk? > > Regards > VP > > --- > > gcc/ChangeLog > > 2013-08-20 Vidya Praveen > > * config/aarch64/aarch64.md (unspec): Add UNSPEC_SISD_SSHL, > UNSPEC_SISD_USHL, UNSPEC_USHL_2S, UNSPEC_SSHL_2S, UNSPEC_SISD_NEG. > (3_insn): Remove. > (aarch64_ashl_sisd_or_int_3): New Pattern. > (aarch64_lshr_sisd_or_int_3): Likewise. > (aarch64_ashr_sisd_or_int_3): Likewise. > (define_split for aarch64_lshr_sisd_or_int_di3): Likewise. > (define_split for aarch64_lshr_sisd_or_int_si3): Likewise. > (define_split for aarch64_ashr_sisd_or_int_di3): Likewise. > (define_split for aarch64_ashr_sisd_or_int_si3): Likewise. > (aarch64_sisd_ushl, aarch64_sisd_sshl): Likewise. > (aarch64_ushl_2s, aarch64_sshl_2s, aarch64_sisd_neg_qi): Likewise. > (ror3_insn): Likewise. > * config/aarch64/predicates.md (aarch64_simd_register): New. > > gcc/testsuite/ChangeLog > > 2013-08-20 Vidya Praveen > > * gcc.target/aarch64/scalar_shift_1.c: New. > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 5312a79..07349c6 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -88,11 +88,16 @@ UNSPEC_NOP UNSPEC_PRLG_STK UNSPEC_RBIT + UNSPEC_SISD_NEG + UNSPEC_SISD_SSHL + UNSPEC_SISD_USHL + UNSPEC_SSHL_2S UNSPEC_ST2 UNSPEC_ST3 UNSPEC_ST4 UNSPEC_TLS UNSPEC_TLSDESC + UNSPEC_USHL_2S UNSPEC_VSTRUCTDUMMY ]) @@ -3183,13 +3188,182 @@ } ) -(define_insn "*3_insn" +;; Logical left shift using SISD or Integer instruction +(define_insn "*aarch64_ashl_sisd_or_int_3" + [(set (match_operand:GPI 0 "register_operand" "=w,w,r") + (ashift:GPI + (match_operand:GPI 1 "register_operand" "w,w,r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "Us,w,rUs")))] + "" + "@ + shl\t%0, %1, %2 + ushl\t%0, %1, %2 + lsl\t%0, %1, %2" + [(set_attr "simd" "yes,yes,no") + (set_attr "simd_type" "simd_shift_imm,simd_shift,*") + (set_attr "simd_mode" ",,*") + (set_attr "v8type" "*,*,shift") + (set_attr "type" "*,*,shift") + (set_attr "mode" "*,*,")] +) + +;; Logical right shift using SISD or Integer instruction +(define_insn "*aarch64_lshr_sisd_or_int_3" + [(set (match_operand:GPI 0 "register_operand" "=w,w,r") + (lshiftrt:GPI + (match_operand:GPI 1 "register_operand" "w,w,r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "Us,w,rUs")))] + "" + "@ + ushr\t%0, %1, %2 + # + lsr\t%0, %1, %2" + [(set_attr "simd" "yes,yes,no") + (set_attr "simd_type" "simd_shift_imm,simd_shift,*") + (set_attr "simd_mode" ",,*") + (set_attr "v8type" "*,*,shift") + (set_attr "type" "*,*,shift") + (set_attr "mode" "*,*,")] +) + +(define_split + [(set (match_operand:DI 0 "aarch64_simd_register") + (lshiftrt:DI + (match_operand:DI 1 "aarch64_simd_register") + (match_operand:QI 2 "aarch64_simd_register")))] + "TARGET_SIMD && reload_completed" + [(set (match_dup 2) + (unspec:QI [(match_dup 2)] UNSPEC_SISD_NEG)) + (set (match_dup 0) + (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_SISD_USHL))] + "" +) + +(define_split + [(set (match_operand:SI 0 "aarch64_simd_register") + (lshiftrt:SI + (match_operand:SI 1 "aarch64_simd_register") + (match_operand:QI 2 "aarch64_simd_register")))] + "TARGET_SIMD && reload_completed" + [(set (match_dup 2) + (unspec:QI [(match_dup 2)] UNSPEC_SISD_NEG)) + (set (match_dup 0) + (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_USHL_2S))] + "" +) + +;; Arithmetic right shift using SISD or Integer instruction +(define_insn "*aarch64_ashr_sisd_or_int_3" + [(set (match_operand:GPI 0 "register_operand" "=w,w,r") + (ashiftrt:GPI + (match_operand:GPI 1 "register_operand" "w,w,r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "Us,w,rUs")))] + "" + "@ + sshr\t%0, %1, %2 + # + asr\t%0, %1, %2" + [(set_attr "simd" "yes,yes,no") + (set_attr "simd_type" "simd_shift_imm,simd_shift,*") + (set_attr "simd_mode" ",,*") + (set_attr "v8type" "*,*,shift") + (set_attr "type" "*,*,shift") + (set_attr "mode" "*,*,")] +) + +(define_split + [(set (match_operand:DI 0 "aarch64_simd_register") + (ashiftrt:DI + (match_operand:DI 1 "aarch64_simd_register") + (match_operand:QI 2 "aarch64_simd_register")))] + "TARGET_SIMD && reload_completed" + [(set (match_dup 2) + (unspec:QI [(match_dup 2)] UNSPEC_SISD_NEG)) + (set (match_dup 0) + (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_SISD_SSHL))] + "" +) + +(define_split + [(set (match_operand:SI 0 "aarch64_simd_register") + (ashiftrt:SI + (match_operand:SI 1 "aarch64_simd_register") + (match_operand:QI 2 "aarch64_simd_register")))] + "TARGET_SIMD && reload_completed" + [(set (match_dup 2) + (unspec:QI [(match_dup 2)] UNSPEC_SISD_NEG)) + (set (match_dup 0) + (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_SSHL_2S))] + "" +) + +(define_insn "*aarch64_sisd_ushl" + [(set (match_operand:DI 0 "register_operand" "=w") + (unspec:DI [(match_operand:DI 1 "register_operand" "w") + (match_operand:QI 2 "register_operand" "w")] + UNSPEC_SISD_USHL))] + "TARGET_SIMD" + "ushl\t%d0, %d1, %d2" + [(set_attr "simd" "yes") + (set_attr "simd_type" "simd_shift") + (set_attr "simd_mode" "DI")] +) + +(define_insn "*aarch64_ushl_2s" + [(set (match_operand:SI 0 "register_operand" "=w") + (unspec:SI [(match_operand:SI 1 "register_operand" "w") + (match_operand:QI 2 "register_operand" "w")] + UNSPEC_USHL_2S))] + "TARGET_SIMD" + "ushl\t%0.2s, %1.2s, %2.2s" + [(set_attr "simd" "yes") + (set_attr "simd_type" "simd_shift") + (set_attr "simd_mode" "DI")] +) + +(define_insn "*aarch64_sisd_sshl" + [(set (match_operand:DI 0 "register_operand" "=w") + (unspec:DI [(match_operand:DI 1 "register_operand" "w") + (match_operand:QI 2 "register_operand" "w")] + UNSPEC_SISD_SSHL))] + "TARGET_SIMD" + "sshl\t%d0, %d1, %d2" + [(set_attr "simd" "yes") + (set_attr "simd_type" "simd_shift") + (set_attr "simd_mode" "DI")] +) + +(define_insn "*aarch64_sshl_2s" + [(set (match_operand:SI 0 "register_operand" "=w") + (unspec:SI [(match_operand:SI 1 "register_operand" "w") + (match_operand:QI 2 "register_operand" "w")] + UNSPEC_SSHL_2S))] + "TARGET_SIMD" + "sshl\t%0.2s, %1.2s, %2.2s" + [(set_attr "simd" "yes") + (set_attr "simd_type" "simd_shift") + (set_attr "simd_mode" "DI")] +) + +(define_insn "*aarch64_sisd_neg_qi" + [(set (match_operand:QI 0 "register_operand" "=w") + (unspec:QI [(match_operand:QI 1 "register_operand" "w")] + UNSPEC_SISD_NEG))] + "TARGET_SIMD" + "neg\t%d0, %d1" + [(set_attr "simd" "yes") + (set_attr "simd_type" "simd_negabs") + (set_attr "simd_mode" "QI")] +) + +;; Rotate right +(define_insn "*ror3_insn" [(set (match_operand:GPI 0 "register_operand" "=r") - (SHIFT:GPI - (match_operand:GPI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "rUs")))] + (rotatert:GPI + (match_operand:GPI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "rUs")))] "" - "\\t%0, %1, %2" + "ror\\t%0, %1, %2" [(set_attr "v8type" "shift") (set_attr "type" "shift") (set_attr "mode" "")] diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 3e2b6b3..dbc9082 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -26,6 +26,11 @@ && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))) ) +(define_predicate "aarch64_simd_register" + (and (match_code "reg") + (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS") + (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS")))) + (define_predicate "aarch64_reg_or_zero" (and (match_code "reg,subreg,const_int") (ior (match_operand 0 "register_operand") diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c new file mode 100644 index 0000000..7cb17f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c @@ -0,0 +1,263 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-inline -save-temps" } */ + +extern void abort (); + +#define force_simd_di(v) asm volatile ("mov %d0, %1.d[0]" :"=w" (v) :"w" (v) :) +#define force_simd_si(v) asm volatile ("mov %s0, %1.s[0]" :"=w" (v) :"w" (v) :) + +typedef unsigned long long int UInt64x1; +typedef long long int Int64x1; +typedef unsigned int UInt32x1; +typedef int Int32x1; + +UInt64x1 +test_lshift_left_sisd_di (UInt64x1 b, UInt64x1 c) +{ + UInt64x1 a; + + force_simd_di (b); + force_simd_di (c); + a = b << 8; + a = a << c; + force_simd_di (a); + return a; +} +/* { dg-final { scan-assembler "shl\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */ +/* { dg-final { scan-assembler "ushl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */ + +UInt32x1 +test_lshift_left_sisd_si (UInt32x1 b, UInt32x1 c) +{ + UInt32x1 a; + + force_simd_si (b); + force_simd_si (c); + a = b << 4; + a = a << c; + force_simd_si (a); + return a; +} +/* { dg-final { scan-assembler "shl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */ +/* "ushl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" (counted later) */ + +UInt64x1 +test_lshift_right_sisd_di (UInt64x1 b, UInt64x1 c) +{ + UInt64x1 a; + + force_simd_di (b); + force_simd_di (c); + a = b >> 8; + a = a >> c; + force_simd_di (a); + return a; +} +/* { dg-final { scan-assembler "ushr\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */ +/* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */ +/* { dg-final { scan-assembler "ushl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */ + +UInt64x1 +test_lshift_right_sisd_si (UInt32x1 b, UInt32x1 c) +{ + UInt32x1 a; + + force_simd_si (b); + force_simd_si (c); + a = b >> 4; + a = a >> c; + force_simd_si (a); + return a; +} +/* { dg-final { scan-assembler "ushr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */ +/* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */ +/* { dg-final { scan-assembler-times "ushl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" 2 } } */ + +Int64x1 +test_ashift_right_sisd_di (Int64x1 b, Int64x1 c) +{ + Int64x1 a; + + force_simd_di (b); + force_simd_di (c); + a = b >> 8; + a = a >> c; + force_simd_di (a); + return a; +} +/* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */ +/* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */ +/* { dg-final { scan-assembler "sshl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */ + +Int32x1 +test_ashift_right_sisd_si (Int32x1 b, Int32x1 c) +{ + Int32x1 a; + + force_simd_si (b); + force_simd_si (c); + a = b >> 4; + a = a >> c; + force_simd_si (a); + return a; +} +/* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */ +/* { dg-final { scan-assembler-times "neg\td\[0-9\]+,\ d\[0-9\]+" 4 } } */ +/* { dg-final { scan-assembler "sshl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" } } */ + + +/* The following are to make sure if the integer instructions lsl/lsr/asr are + generated in non-vector scenarios */ + +UInt64x1 +test_lshift_left_int_di (UInt64x1 b, UInt64x1 c) +{ + UInt64x1 a; + + a = b << 8; + a = a << c; + return a; +} +/* { dg-final { scan-assembler "lsl\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */ +/* { dg-final { scan-assembler "lsl\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */ + +UInt32x1 +test_lshift_left_int_si (UInt32x1 b, UInt32x1 c) +{ + UInt32x1 a; + + a = b << 4; + a = a << c; + return a; +} +/* { dg-final { scan-assembler "lsl\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */ +/* { dg-final { scan-assembler "lsl\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */ + +UInt64x1 +test_lshift_right_int_di (UInt64x1 b, UInt64x1 c) +{ + UInt64x1 a; + + a = b >> 8; + a = a >> c; + return a; +} +/* { dg-final { scan-assembler "lsr\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */ +/* { dg-final { scan-assembler "lsr\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */ + +UInt32x1 +test_lshift_right_int_si (UInt32x1 b, UInt32x1 c) +{ + UInt32x1 a; + + a = b >> 4; + a = a >> c; + return a; +} +/* { dg-final { scan-assembler "lsr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */ +/* { dg-final { scan-assembler "lsr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */ + +Int64x1 +test_ashift_right_int_di (Int64x1 b, Int64x1 c) +{ + Int64x1 a; + + a = b >> 8; + a = a >> c; + return a; +} +/* { dg-final { scan-assembler "asr\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */ +/* { dg-final { scan-assembler "asr\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */ + +Int32x1 +test_ashift_right_int_si (Int32x1 b, Int32x1 c) +{ + Int32x1 a; + + a = b >> 4; + a = a >> c; + return a; +} +/* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */ +/* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */ + +Int64x1 +test_corners_sisd_di (Int64x1 b) +{ + force_simd_di (b); + b = b >> 63; + b = b >> 0; + b += b >> 65; /* { dg-warning "right shift count >= width of type" } */ + force_simd_di (b); + + return b; +} +/* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 63" } } */ +/* { dg-final { scan-assembler "shl\td\[0-9\]+,\ d\[0-9\]+,\ 1" } } */ + +Int32x1 +test_corners_sisd_si (Int32x1 b) +{ + force_simd_si (b); + b = b >> 31; + b = b >> 0; + b += b >> 33; /* { dg-warning "right shift count >= width of type" } */ + force_simd_si (b); + + return b; +} +/* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 31" } } */ +/* { dg-final { scan-assembler "shl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 1" } } */ + + + +#define CHECK(var,val) \ +do \ + { \ + if (var != val) \ + abort(); \ + } \ +while(0) + +UInt64x1 x = 0xC01dDeadBeefFaceull; +UInt32x1 y = 0xDeadBeef; + +int +main () +{ + x = test_lshift_left_sisd_di (x, 8); + CHECK (x, 0xdeadbeefface0000ull); + x = test_lshift_right_int_di (x, 8); + CHECK (x, 0x0000deadbeeffaceull); + x = test_lshift_right_sisd_di (x, 8); + CHECK (x, 0x00000000deadbeefull); + x = test_lshift_left_int_di (x, 8); + CHECK (x, 0x0000deadbeef0000ull); + x = ~x; + x = test_ashift_right_int_di (x, 8); + CHECK (x, 0xffffffff21524110ull); + x = test_ashift_right_sisd_di (x, 8); + CHECK (x, 0xffffffffffff2152ull); + x = test_corners_sisd_di (x); + CHECK (x, 0xfffffffffffffffeull); + + y = test_lshift_left_sisd_si (y, 4); + CHECK (y, 0xadbeef00); + y = test_lshift_right_int_si (y, 4); + CHECK (y, 0x00adbeef); + y = test_lshift_right_sisd_si (y, 4); + CHECK (y, 0x0000adbe); + y = test_lshift_left_int_si (y, 4); + CHECK (y, 0x00adbe00); + y = ~y; + y = test_ashift_right_int_si (y, 4); + CHECK (y, 0xffff5241); + y = test_ashift_right_sisd_si (y, 4); + CHECK (y, 0xffffff52); + y = test_corners_sisd_si (y); + CHECK (y, 0xfffffffe); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */