From patchwork Wed Aug 14 14:51:31 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 267142 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C0A6F2C0108 for ; Thu, 15 Aug 2013 00:51:56 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A26564A13D; Wed, 14 Aug 2013 16:51:54 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CS8ui7cvh6Bk; Wed, 14 Aug 2013 16:51:54 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 803A54A14C; Wed, 14 Aug 2013 16:51:52 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 503264A14D for ; Wed, 14 Aug 2013 16:51:46 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KSSyVZ4hZesb for ; Wed, 14 Aug 2013 16:51:41 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=SKIP(-1.5) (only DNSBL check requested) Received: from mail-qc0-f181.google.com (mail-qc0-f181.google.com [209.85.216.181]) by theia.denx.de (Postfix) with ESMTPS id 31E4D4A14C for ; Wed, 14 Aug 2013 16:51:37 +0200 (CEST) Received: by mail-qc0-f181.google.com with SMTP id k15so4895017qcv.40 for ; Wed, 14 Aug 2013 07:51:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=99QYbecm9K3jwRtr+bK4MD6wWMXTIAcjDVXQZ6Oui30=; b=cREdTi5DWusfTAzbjXs9/Pg80dpZ91VddSff9vzbQIqwSMlThiBJbOyyjHcbjO/6v2 7JQQvcg3EYQ05pXUFyKmoSKOVgdrcr22wZoWrZhd/wvqHa5iUUiShTzdRJ1MQWnWEmne C8Ki5r2S3CICziO1hMLJMGnFB9xdqeOo5vEukPZnj5ackyOn5AedZd0AVAmiDKRgjAdj NG1p6xHT2OZ0ssby0nSD72PpIDOcS/A3RZPvAWVYiGo/bY9ZA/AHzGsuXHpm/s7fDJPx Iwo19n+hfuCy6RJ/laznZ6bk3LFasBU/6lvgD9sIdioyAGQj0Fv76kD2gmZFzib0Vdd9 PC8w== X-Received: by 10.49.75.103 with SMTP id b7mr5371108qew.85.1376491896478; Wed, 14 Aug 2013 07:51:36 -0700 (PDT) Received: from localhost.localdomain (cpe-065-184-250-089.ec.res.rr.com. [65.184.250.89]) by mx.google.com with ESMTPSA id m5sm31326912qaa.13.2013.08.14.07.51.35 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 14 Aug 2013 07:51:35 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Date: Wed, 14 Aug 2013 10:51:31 -0400 Message-Id: <1376491891-9228-1-git-send-email-trini@ti.com> X-Mailer: git-send-email 1.7.9.5 Cc: Steve Kipisz , Enric Balletbo i Serra , Lars Poeschel Subject: [U-Boot] [PATCH v2] am335x:Handle worst case scenario for Errata 1.0.24 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Steve Kipisz In Errata 1.0.24, if the board is running at OPP50 and has a warm reset, the boot ROM sets the frequencies for OPP100. This patch attempts to drop the frequencies back to OPP50 as soon as possible in the SPL. Then later the voltages and frequencies up set higher. Cc: Enric Balletbo i Serra Cc: Lars Poeschel Signed-off-by: Steve Kipisz [trini: Adapt to current framework] Signed-off-by: Tom Rini --- Changes in v2: - Address Dan Murphy's comments --- arch/arm/cpu/armv7/am33xx/board.c | 2 + arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 72 ++++++++++++++-------- arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 3 + arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 + board/ti/am335x/board.c | 12 ++++ include/configs/pcm051.h | 1 + include/power/tps65217.h | 1 + 7 files changed, 68 insertions(+), 24 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 88e2093..e94b038 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -150,6 +150,8 @@ int arch_misc_init(void) */ __weak void am33xx_spl_board_init(void) { + mpu_pll_config_val(CONFIG_SYS_MPUCLK); + core_pll_config(OPP_100); } void rtc32k_enable(void) diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index fb3fb43..f623004 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -42,12 +42,17 @@ /* Core PLL Fdll = 1 GHZ, */ #define COREPLL_M 1000 +#define COREPLL_M_OPP50 50 #define COREPLL_N (OSC-1) #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ #define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */ +#define COREPLL_M4_OPP50 1 +#define COREPLL_M5_OPP50 1 +#define COREPLL_M6_OPP50 1 + /* * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll * frequency needs to be set to 960 MHZ. Hence, @@ -266,12 +271,7 @@ void mpu_pll_config_val(int mpull_m) ; } -static void mpu_pll_config(void) -{ - mpu_pll_config_val(CONFIG_SYS_MPUCLK); -} - -static void core_pll_config(void) +void core_pll_config(int opp) { u32 clkmode, clksel, div_m4, div_m5, div_m6; @@ -285,29 +285,53 @@ static void core_pll_config(void) writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore); while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS) - ; + ; + if (opp == OPP_50) { + clksel = clksel & (~CLK_SEL_MASK); + clksel = clksel | ((COREPLL_M_OPP50 << CLK_SEL_SHIFT) + | COREPLL_N); + writel(clksel, &cmwkup->clkseldpllcore); - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N); - writel(clksel, &cmwkup->clkseldpllcore); + div_m4 = div_m4 & ~CLK_DIV_MASK; + div_m4 = div_m4 | COREPLL_M4_OPP50; + writel(div_m4, &cmwkup->divm4dpllcore); - div_m4 = div_m4 & ~CLK_DIV_MASK; - div_m4 = div_m4 | COREPLL_M4; - writel(div_m4, &cmwkup->divm4dpllcore); + div_m5 = div_m5 & ~CLK_DIV_MASK; + div_m5 = div_m5 | COREPLL_M5_OPP50; + writel(div_m5, &cmwkup->divm5dpllcore); - div_m5 = div_m5 & ~CLK_DIV_MASK; - div_m5 = div_m5 | COREPLL_M5; - writel(div_m5, &cmwkup->divm5dpllcore); + div_m6 = div_m6 & ~CLK_DIV_MASK; + div_m6 = div_m6 | COREPLL_M6_OPP50; + writel(div_m6, &cmwkup->divm6dpllcore); - div_m6 = div_m6 & ~CLK_DIV_MASK; - div_m6 = div_m6 | COREPLL_M6; - writel(div_m6, &cmwkup->divm6dpllcore); + clkmode = clkmode | CLK_MODE_SEL; + writel(clkmode, &cmwkup->clkmoddpllcore); - clkmode = clkmode | CLK_MODE_SEL; - writel(clkmode, &cmwkup->clkmoddpllcore); + while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK) + ; + } else { + clksel = clksel & (~CLK_SEL_MASK); + clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N); + writel(clksel, &cmwkup->clkseldpllcore); + + div_m4 = div_m4 & ~CLK_DIV_MASK; + div_m4 = div_m4 | COREPLL_M4; + writel(div_m4, &cmwkup->divm4dpllcore); + + div_m5 = div_m5 & ~CLK_DIV_MASK; + div_m5 = div_m5 | COREPLL_M5; + writel(div_m5, &cmwkup->divm5dpllcore); + + div_m6 = div_m6 & ~CLK_DIV_MASK; + div_m6 = div_m6 | COREPLL_M6; + writel(div_m6, &cmwkup->divm6dpllcore); + + clkmode = clkmode | CLK_MODE_SEL; + writel(clkmode, &cmwkup->clkmoddpllcore); - while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK) + while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK) ; + } } static void per_pll_config(void) @@ -390,8 +414,8 @@ void enable_emif_clocks(void) */ void pll_init() { - mpu_pll_config(); - core_pll_config(); + mpu_pll_config_val(MPUPLL_M_300); + core_pll_config(OPP_50); per_pll_config(); /* Enable the required interconnect clocks */ diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 789188b..9a480d9 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -11,6 +11,9 @@ #ifndef _CLOCKS_AM33XX_H_ #define _CLOCKS_AM33XX_H_ +#define OPP_50 50 +#define OPP_100 100 + /* MAIN PLL Fdll = 550 MHz, by default */ #ifndef CONFIG_SYS_MPUCLK #define CONFIG_SYS_MPUCLK 550 diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 1340f83..9c7647b 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -27,6 +27,7 @@ void save_omap_boot_params(void); void setup_clocks_for_console(void); void mpu_pll_config_val(int mpull_m); void ddr_pll_config(unsigned int ddrpll_M); +void core_pll_config(int opp); void sdelay(unsigned long); diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index e7f14db..b0fa4b2 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -337,6 +337,15 @@ void am33xx_spl_board_init(void) TPS65217_USB_INPUT_CUR_LIMIT_MASK)) puts("tps65217_reg_write failure\n"); + /* Set DCDC3 (CORE) voltage to 1.125V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1125MV)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set CORE Frequencies to OPP100 */ + core_pll_config(OPP_100); /* Set DCDC2 (MPU) voltage */ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { @@ -395,6 +404,9 @@ void am33xx_spl_board_init(void) /* Second, update the CORE voltage. */ if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) return; + + /* Set CORE Frequencies to OPP100 */ + core_pll_config(OPP_100); } /* Set MPU Frequency to what we detected now that voltages are set */ diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 9b16c47..f4b4d62 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -204,6 +204,7 @@ /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT /* * Place the image at the start of the ROM defined image space. * We limit our size to the ROM-defined downloaded image area, and use the diff --git a/include/power/tps65217.h b/include/power/tps65217.h index f4c7a2b..f3e067d 100644 --- a/include/power/tps65217.h +++ b/include/power/tps65217.h @@ -62,6 +62,7 @@ #define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02 #define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03 +#define TPS65217_DCDC_VOLT_SEL_1125MV 0x09 #define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F #define TPS65217_DCDC_VOLT_SEL_1325MV 0x11