From patchwork Wed Aug 14 14:17:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 267135 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CC5B62C01FB for ; Thu, 15 Aug 2013 00:18:36 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0DF894A143; Wed, 14 Aug 2013 16:18:27 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XSYxYKMV24Qr; Wed, 14 Aug 2013 16:18:26 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6D6024A15A; Wed, 14 Aug 2013 16:18:01 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F1D344A12C for ; Wed, 14 Aug 2013 16:17:47 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3JPRPSQ4mPEn for ; Wed, 14 Aug 2013 16:17:43 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=ERR(-1.5) (only DNSBL check requested) Received: from mail-qa0-f44.google.com (mail-qa0-f44.google.com [209.85.216.44]) by theia.denx.de (Postfix) with ESMTPS id A35764A137 for ; Wed, 14 Aug 2013 16:17:30 +0200 (CEST) Received: by mail-qa0-f44.google.com with SMTP id hu16so1019533qab.3 for ; Wed, 14 Aug 2013 07:17:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=yk6vpBGAIN00pAyZS6JfrHZJb4nMThIyCGVfeK7EAHQ=; b=uXj2+SASFPsK9g9HrWn1Q3WLzlTR4tFVFD9HV6fHaY5rOJ36sB5fZ7XdoDAziAXl3i 3dgd6Y498+pZoP1rMM0KSc/i4r6GxIRhhLtYrVo6GbI5ynT8S8OJW9UxAPGVy+C/S/gj qCFJhs7wnoUXyrAFQqUKKD9KOxjsV60KWh9vZKbUCFH5uljdZ9Z1VONmtjsA66/j1239 5wf/eQkkJTnhAXjzWkOQTfdDrKrwjZAhtDv2hLe9LbP2pUHpoa8SEN92tEubskOFjxo9 bdNfZy+HiHPqZdVyRP8rhw8hZHcyxu70DouC2sa1RslmjN5YBQjkF2EA00Y9giQlET2l oY5Q== X-Received: by 10.229.196.73 with SMTP id ef9mr1192367qcb.85.1376489844692; Wed, 14 Aug 2013 07:17:24 -0700 (PDT) Received: from localhost.localdomain (cpe-065-184-250-089.ec.res.rr.com. [65.184.250.89]) by mx.google.com with ESMTPSA id y1sm51052122qaj.2.2013.08.14.07.17.23 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 14 Aug 2013 07:17:24 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Date: Wed, 14 Aug 2013 10:17:15 -0400 Message-Id: <1376489839-18046-2-git-send-email-trini@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1376489839-18046-1-git-send-email-trini@ti.com> References: <1376489839-18046-1-git-send-email-trini@ti.com> Cc: Greg Guyotte Subject: [U-Boot] [PATCH v2 2/6] drivers/power/pmic: Add tps65217 driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Greg Guyotte Add a driver for the TPS65217 PMIC that is found in the Beaglebone family of boards. Signed-off-by: Greg Guyotte [trini: Split and rework Greg's changes into new drivers/power framework] Signed-off-by: Tom Rini --- Changes in v2: - Address Dan's comments - Change to SPDX license tag - Add TRM link in the header Signed-off-by: Tom Rini --- drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65217.c | 109 ++++++++++++++++++++++++++++++++++++ include/power/tps65217.h | 79 ++++++++++++++++++++++++++ 3 files changed, 189 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps65217.c create mode 100644 include/power/tps65217.h diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index f054470..ac2b625 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -13,6 +13,7 @@ COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o +COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/power/pmic/pmic_tps65217.c b/drivers/power/pmic/pmic_tps65217.c new file mode 100644 index 0000000..36e9024 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65217.c @@ -0,0 +1,109 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/** + * tps65217_reg_read() - Generic function that can read a TPS65217 register + * @src_reg: Source register address + * @src_val: Address of destination variable + * @return: 0 for success, not 0 on failure. + */ +int tps65217_reg_read(uchar src_reg, uchar *src_val) +{ + return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1); +} + +/** + * tps65217_reg_write() - Generic function that can write a TPS65217 PMIC + * register or bit field regardless of protection + * level. + * + * @prot_level: Register password protection. Use + * TPS65217_PROT_LEVEL_NONE, + * TPS65217_PROT_LEVEL_1 or TPS65217_PROT_LEVEL_2 + * @dest_reg: Register address to write. + * @dest_val: Value to write. + * @mask: Bit mask (8 bits) to be applied. Function will only + * change bits that are set in the bit mask. + * + * @return: 0 for success, not 0 on failure, as per the i2c API + */ +int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask) +{ + uchar read_val; + uchar xor_reg; + int ret; + + /* + * If we are affecting only a bit field, read dest_reg and apply the + * mask + */ + if (mask != TPS65217_MASK_ALL_BITS) { + ret = i2c_read(TPS65217_CHIP_PM, dest_reg, 1, &read_val, 1); + if (ret) + return ret; + read_val &= (~mask); + read_val |= (dest_val & mask); + dest_val = read_val; + } + + if (prot_level > 0) { + xor_reg = dest_reg ^ TPS65217_PASSWORD_UNLOCK; + ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + } + + ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + + if (prot_level == TPS65217_PROT_LEVEL_2) { + ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + + ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + } + + return 0; +} + +/** + * tps65217_voltage_update() - Function to change a voltage level, as this + * is a multi-step process. + * @dc_cntrl_reg: DC voltage control register to change. + * @volt_sel: New value for the voltage register + * @return: 0 for success, not 0 on failure. + */ +int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel) +{ + if ((dc_cntrl_reg != TPS65217_DEFDCDC1) && + (dc_cntrl_reg != TPS65217_DEFDCDC2) && + (dc_cntrl_reg != TPS65217_DEFDCDC3)) + return 1; + + /* set voltage level */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, dc_cntrl_reg, volt_sel, + TPS65217_MASK_ALL_BITS)) + return 1; + + /* set GO bit to initiate voltage transition */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFSLEW, + TPS65217_DCDC_GO, TPS65217_DCDC_GO)) + return 1; + + return 0; +} diff --git a/include/power/tps65217.h b/include/power/tps65217.h new file mode 100644 index 0000000..f4c7a2b --- /dev/null +++ b/include/power/tps65217.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the TRM at http://www.ti.com/product/tps65217a + */ + +#ifndef __POWER_TPS65217_H__ +#define __POWER_TPS65217_H__ + +/* I2C chip address */ +#define TPS65217_CHIP_PM 0x24 + +/* Registers */ +#define TPS65217_CHIPID 0x00 +#define TPS65217_POWER_PATH 0x01 +#define TPS65217_INTERRUPT 0x02 +#define TPS65217_CHGCONFIG0 0x03 +#define TPS65217_CHGCONFIG1 0x04 +#define TPS65217_CHGCONFIG2 0x05 +#define TPS65217_CHGCONFIG3 0x06 +#define TPS65217_WLEDCTRL1 0x07 +#define TPS65217_WLEDCTRL2 0x08 +#define TPS65217_MUXCTRL 0x09 +#define TPS65217_STATUS 0x0A +#define TPS65217_PASSWORD 0x0B +#define TPS65217_PGOOD 0x0C +#define TPS65217_DEFPG 0x0D +#define TPS65217_DEFDCDC1 0x0E +#define TPS65217_DEFDCDC2 0x0F +#define TPS65217_DEFDCDC3 0x10 +#define TPS65217_DEFSLEW 0x11 +#define TPS65217_DEFLDO1 0x12 +#define TPS65217_DEFLDO2 0x13 +#define TPS65217_DEFLS1 0x14 +#define TPS65217_DEFLS2 0x15 +#define TPS65217_ENABLE 0x16 +#define TPS65217_DEFUVLO 0x18 +#define TPS65217_SEQ1 0x19 +#define TPS65217_SEQ2 0x1A +#define TPS65217_SEQ3 0x1B +#define TPS65217_SEQ4 0x1C +#define TPS65217_SEQ5 0x1D +#define TPS65217_SEQ6 0x1E + +#define TPS65217_PROT_LEVEL_NONE 0x00 +#define TPS65217_PROT_LEVEL_1 0x01 +#define TPS65217_PROT_LEVEL_2 0x02 + +#define TPS65217_PASSWORD_LOCK_FOR_WRITE 0x00 +#define TPS65217_PASSWORD_UNLOCK 0x7D + +#define TPS65217_DCDC_GO 0x80 + +#define TPS65217_MASK_ALL_BITS 0xFF + +#define TPS65217_USB_INPUT_CUR_LIMIT_MASK 0x03 +#define TPS65217_USB_INPUT_CUR_LIMIT_100MA 0x00 +#define TPS65217_USB_INPUT_CUR_LIMIT_500MA 0x01 +#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02 +#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03 + +#define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F +#define TPS65217_DCDC_VOLT_SEL_1325MV 0x11 + +#define TPS65217_LDO_MASK 0x1F +#define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06 +#define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F + +#define TPS65217_PWR_SRC_USB_BITMASK 0x4 +#define TPS65217_PWR_SRC_AC_BITMASK 0x8 + +int tps65217_reg_read(uchar src_reg, uchar *src_val); +int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask); +int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); +#endif /* __POWER_TPS65217_H__ */