From patchwork Tue Aug 13 20:57:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 266918 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 8FCB82C016C for ; Wed, 14 Aug 2013 06:57:28 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; q= dns; s=default; b=xQe9Jwq5i6gNySuducsBMJimOgcB8t1894ZeyDoaPJhK3u Pb5QRldsp5p5rWIMotmLJhnyPkZt4cieITwN/nanV/zgk5ajD4DtFGLpJJ65300E vVqNTxU7faXmT7wfI8P+wr1o9vuy87vfweW6tpi2zBmfyeKhmRd/+VDtsJK7M= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; s= default; bh=20AZBucnbuyzhz/BbtNL/xx6F84=; b=Bsp0z637bnpOmPXiiC7e BFndCSM3ZZpTMezAbKtZwaflp201HoLYZDCnb94ZLPY7pFo0SwNfseF/zZAyN5pd u/lQ1O5MRTzeVEZgR+aH4dvx8n4n+7aK7lapird+2ihoUDffW3q1Vvs9qwJtbqcf yZqm8FpntBGlFLyIRzl+eYk= Received: (qmail 30402 invoked by alias); 13 Aug 2013 20:57:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 30388 invoked by uid 89); 13 Aug 2013 20:57:21 -0000 X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_YE, SPF_PASS autolearn=ham version=3.3.2 Received: from mail-oa0-f53.google.com (HELO mail-oa0-f53.google.com) (209.85.219.53) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Tue, 13 Aug 2013 20:57:19 +0000 Received: by mail-oa0-f53.google.com with SMTP id k18so12265363oag.12 for ; Tue, 13 Aug 2013 13:57:18 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.182.72.234 with SMTP id g10mr2874091obv.60.1376427438080; Tue, 13 Aug 2013 13:57:18 -0700 (PDT) Received: by 10.182.111.167 with HTTP; Tue, 13 Aug 2013 13:57:18 -0700 (PDT) Date: Tue, 13 Aug 2013 22:57:18 +0200 Message-ID: Subject: [PATCH, i386]: Correct sse3_monitor and sse2_maskmovdqu patterns for Pmode != word_mode From: Uros Bizjak To: "gcc-patches@gcc.gnu.org" X-Virus-Found: No Hello! These two insns have implicit address operands, so when Pmode != word_mode (x32 with -maddress-mode=short) we have to instruct the linker to emit 0x67 address override prefix. The patch also changes *sse3_monitor pattern to emit mnemonic with implicit operands, to avoid duplicating operands in reverse order for Intel syntax. 2013-08-13 Uros Bizjak * config/i386/sse.md (*sse2_maskmovdqu): Emit addr32 prefix when Pmode != word_mode. Add length_address attribute. (sse3_monitor_): Merge from sse3_monitor and sse3_monitor64_ insn patterns. Emit addr32 prefix when Pmode != word_mode. Update insn length attribute. * config/i386/i386.c (ix86_option_override_internal): Update ix86_gen_monitor selection for merged sse3_monitor insn. Patch was tested on x86_64-pc-linux-gnu {,-m32} and committed to mainline SVN. Uros. Index: i386.c =================================================================== --- i386.c (revision 201689) +++ i386.c (working copy) @@ -4170,24 +4170,19 @@ ix86_option_override_internal (bool main_args_p) ix86_gen_leave = gen_leave_rex64; if (Pmode == DImode) { - ix86_gen_monitor = gen_sse3_monitor64_di; ix86_gen_tls_global_dynamic_64 = gen_tls_global_dynamic_64_di; ix86_gen_tls_local_dynamic_base_64 = gen_tls_local_dynamic_base_64_di; } else { - ix86_gen_monitor = gen_sse3_monitor64_si; ix86_gen_tls_global_dynamic_64 = gen_tls_global_dynamic_64_si; ix86_gen_tls_local_dynamic_base_64 = gen_tls_local_dynamic_base_64_si; } } else - { - ix86_gen_leave = gen_leave; - ix86_gen_monitor = gen_sse3_monitor; - } + ix86_gen_leave = gen_leave; if (Pmode == DImode) { @@ -4199,6 +4194,7 @@ ix86_option_override_internal (bool main_args_p) ix86_gen_allocate_stack_worker = gen_allocate_stack_worker_probe_di; ix86_gen_adjust_stack_and_probe = gen_adjust_stack_and_probedi; ix86_gen_probe_stack_range = gen_probe_stack_rangedi; + ix86_gen_monitor = gen_sse3_monitor_di; } else { @@ -4210,6 +4206,7 @@ ix86_option_override_internal (bool main_args_p) ix86_gen_allocate_stack_worker = gen_allocate_stack_worker_probe_si; ix86_gen_adjust_stack_and_probe = gen_adjust_stack_and_probesi; ix86_gen_probe_stack_range = gen_probe_stack_rangesi; + ix86_gen_monitor = gen_sse3_monitor_si; } #ifdef USE_IX86_CLD Index: sse.md =================================================================== --- sse.md (revision 201689) +++ sse.md (working copy) @@ -7731,9 +7731,17 @@ (mem:V16QI (match_dup 0))] UNSPEC_MASKMOV))] "TARGET_SSE2" - "%vmaskmovdqu\t{%2, %1|%1, %2}" +{ + /* We can't use %^ here due to ASM_OUTPUT_OPCODE processing + that requires %v to be at the beginning of the opcode name. */ + if (Pmode != word_mode) + fputs ("\taddr32", asm_out_file); + return "%vmaskmovdqu\t{%2, %1|%1, %2}"; +} [(set_attr "type" "ssemov") (set_attr "prefix_data16" "1") + (set (attr "length_address") + (symbol_ref ("Pmode != word_mode"))) ;; The implicit %rdi operand confuses default length_vex computation. (set (attr "length_vex") (symbol_ref ("3 + REX_SSE_REGNO_P (REGNO (operands[2]))"))) @@ -7781,26 +7789,18 @@ "mwait" [(set_attr "length" "3")]) -(define_insn "sse3_monitor" - [(unspec_volatile [(match_operand:SI 0 "register_operand" "a") - (match_operand:SI 1 "register_operand" "c") - (match_operand:SI 2 "register_operand" "d")] - UNSPECV_MONITOR)] - "TARGET_SSE3 && !TARGET_64BIT" - "monitor\t%0, %1, %2" - [(set_attr "length" "3")]) - -(define_insn "sse3_monitor64_" +(define_insn "sse3_monitor_" [(unspec_volatile [(match_operand:P 0 "register_operand" "a") (match_operand:SI 1 "register_operand" "c") (match_operand:SI 2 "register_operand" "d")] UNSPECV_MONITOR)] - "TARGET_SSE3 && TARGET_64BIT" + "TARGET_SSE3" ;; 64bit version is "monitor %rax,%rcx,%rdx". But only lower 32bits in ;; RCX and RDX are used. Since 32bit register operands are implicitly ;; zero extended to 64bit, we only need to set up 32bit registers. - "monitor" - [(set_attr "length" "3")]) + "%^monitor" + [(set (attr "length") + (symbol_ref ("(Pmode != word_mode) + 3")))]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;