From patchwork Mon Aug 12 19:28:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 266627 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 9E59D2C0121 for ; Tue, 13 Aug 2013 05:29:10 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; q=dns; s=default; b=psaQzryy8gISC6umSE w5JBK3fe7NiFhe6F/sto2DvZ3bJxGxms+blDfk8mogNMZdaC8blMIaD3I9oh8JUA z7iQtWvSYfZmM088F+NSYUks18cEgAlzLHHDCg/ax6+xE3BWJmPpJEKIYPBPMlNE HME5iFVvhIR42fPuKSaJh1/kg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; s=default; bh=oFlEfuLMfZ5KbvHVER5QbLUe Dt4=; b=eUX/3y8fIg76w1fmvC3xBo3RPeYIMoQMvUg13f/dXSLq1ZvaAx0kj8SL vCaqDv2b5Lf0nN4FbbIaV1iNQHBTLADPjxrx/BM2nTlN8+yC1ELD2ZdL4ijhNSBu 1EnYwrJNCV9RcHI3NdPUqxvrYxVnwWeiaNY8oXwdvn+0G7yWeVw= Received: (qmail 32362 invoked by alias); 12 Aug 2013 19:29:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 32347 invoked by uid 89); 12 Aug 2013 19:29:01 -0000 X-Spam-SWARE-Status: No, score=-3.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, KHOP_THREADED, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_YE, SPF_PASS autolearn=ham version=3.3.2 Received: from mail-ob0-f174.google.com (HELO mail-ob0-f174.google.com) (209.85.214.174) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Mon, 12 Aug 2013 19:29:00 +0000 Received: by mail-ob0-f174.google.com with SMTP id wd6so6913982obb.19 for ; Mon, 12 Aug 2013 12:28:58 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.60.60.5 with SMTP id d5mr564571oer.0.1376335738775; Mon, 12 Aug 2013 12:28:58 -0700 (PDT) Received: by 10.182.111.167 with HTTP; Mon, 12 Aug 2013 12:28:58 -0700 (PDT) In-Reply-To: References: Date: Mon, 12 Aug 2013 21:28:58 +0200 Message-ID: Subject: Re: [PATCH] x86-64 gcc generate wrong assembly instruction movabs for intel syntax From: Uros Bizjak To: Anna Tikhonova Cc: "gcc-patches@gcc.gnu.org" , Perez Read X-Virus-Found: No On Mon, Aug 12, 2013 at 11:04 AM, Anna Tikhonova wrote: > Also, there should be an issue with -masm=intel for sse3_monitor. Please see > attached patch. We can just use "monitor" with implicit operands here, like in attached patch. It should handle 32bit, 64bit and x32 targets with ATT and Intel syntax. Uros. Index: i386.c =================================================================== --- i386.c (revision 201667) +++ i386.c (working copy) @@ -4170,24 +4170,19 @@ ix86_gen_leave = gen_leave_rex64; if (Pmode == DImode) { - ix86_gen_monitor = gen_sse3_monitor64_di; ix86_gen_tls_global_dynamic_64 = gen_tls_global_dynamic_64_di; ix86_gen_tls_local_dynamic_base_64 = gen_tls_local_dynamic_base_64_di; } else { - ix86_gen_monitor = gen_sse3_monitor64_si; ix86_gen_tls_global_dynamic_64 = gen_tls_global_dynamic_64_si; ix86_gen_tls_local_dynamic_base_64 = gen_tls_local_dynamic_base_64_si; } } else - { - ix86_gen_leave = gen_leave; - ix86_gen_monitor = gen_sse3_monitor; - } + ix86_gen_leave = gen_leave; if (Pmode == DImode) { @@ -4199,6 +4194,7 @@ ix86_gen_allocate_stack_worker = gen_allocate_stack_worker_probe_di; ix86_gen_adjust_stack_and_probe = gen_adjust_stack_and_probedi; ix86_gen_probe_stack_range = gen_probe_stack_rangedi; + ix86_gen_monitor = gen_sse3_monitor_di; } else { @@ -4210,6 +4206,7 @@ ix86_gen_allocate_stack_worker = gen_allocate_stack_worker_probe_si; ix86_gen_adjust_stack_and_probe = gen_adjust_stack_and_probesi; ix86_gen_probe_stack_range = gen_probe_stack_rangesi; + ix86_gen_monitor = gen_sse3_monitor_si; } #ifdef USE_IX86_CLD Index: sse.md =================================================================== --- sse.md (revision 201667) +++ sse.md (working copy) @@ -7781,21 +7781,12 @@ "mwait" [(set_attr "length" "3")]) -(define_insn "sse3_monitor" - [(unspec_volatile [(match_operand:SI 0 "register_operand" "a") - (match_operand:SI 1 "register_operand" "c") - (match_operand:SI 2 "register_operand" "d")] - UNSPECV_MONITOR)] - "TARGET_SSE3 && !TARGET_64BIT" - "monitor\t%0, %1, %2" - [(set_attr "length" "3")]) - -(define_insn "sse3_monitor64_" +(define_insn "sse3_monitor_" [(unspec_volatile [(match_operand:P 0 "register_operand" "a") (match_operand:SI 1 "register_operand" "c") (match_operand:SI 2 "register_operand" "d")] UNSPECV_MONITOR)] - "TARGET_SSE3 && TARGET_64BIT" + "TARGET_SSE3" ;; 64bit version is "monitor %rax,%rcx,%rdx". But only lower 32bits in ;; RCX and RDX are used. Since 32bit register operands are implicitly ;; zero extended to 64bit, we only need to set up 32bit registers.