From patchwork Wed Apr 29 18:14:35 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haiying Wang X-Patchwork-Id: 26640 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@bilbo.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id 100A2B7043 for ; Thu, 30 Apr 2009 04:23:32 +1000 (EST) Received: by ozlabs.org (Postfix) id DE508DE3AA; Thu, 30 Apr 2009 04:19:56 +1000 (EST) Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id D6E14DEBA0 for ; Thu, 30 Apr 2009 04:19:56 +1000 (EST) X-Original-To: linuxppc-dev@ozlabs.org Delivered-To: linuxppc-dev@ozlabs.org Received: from az33egw02.freescale.net (az33egw02.freescale.net [192.88.158.103]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "az33egw02.freescale.net", Issuer "Thawte Premium Server CA" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id D2CC4DDE9E for ; Thu, 30 Apr 2009 04:14:29 +1000 (EST) Received: from de01smr01.freescale.net (de01smr01.freescale.net [10.208.0.31]) by az33egw02.freescale.net (8.14.3/az33egw02) with ESMTP id n3TIEHFV006650; Wed, 29 Apr 2009 11:14:18 -0700 (MST) Received: from r54964-12.am.freescale.net (R54964-12.am.freescale.net [10.29.201.229]) by de01smr01.freescale.net (8.13.1/8.13.0) with ESMTP id n3TIEGMr018893; Wed, 29 Apr 2009 13:14:17 -0500 (CDT) Received: from r54964-12.am.freescale.net (localhost.localdomain [127.0.0.1]) by r54964-12.am.freescale.net (8.13.8/8.13.8) with ESMTP id n3TIEgEH027383; Wed, 29 Apr 2009 14:14:42 -0400 Received: (from why@localhost) by r54964-12.am.freescale.net (8.13.8/8.13.8/Submit) id n3TIEfjV027382; Wed, 29 Apr 2009 14:14:41 -0400 From: Haiying Wang To: linuxppc-dev@ozlabs.org, galak@kernel.crashing.org Subject: [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth Date: Wed, 29 Apr 2009 14:14:35 -0400 Message-Id: <12410288811793-git-send-email-Haiying.Wang@freescale.com> X-Mailer: git-send-email 1.5.3.rc3.13.g7ab3c In-Reply-To: <12410288792524-git-send-email-Haiying.Wang@freescale.com> References: <1241028878175-git-send-email-Haiying.Wang@freescale.com> <12410288792524-git-send-email-Haiying.Wang@freescale.com> X-Brightmail-Tracker: AAAAAQAAAWE= Cc: Haiying Wang X-BeenThere: linuxppc-dev@ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Change the definition of riscTx and riscRx to unsigned integer instead of enum, and change their values to support 4 risc allocation if the qe has 4 RISC engines. Signed-off-by: Haiying Wang Acked-by: David S. Miller --- drivers/net/ucc_geth.c | 14 +++++++++++--- drivers/net/ucc_geth.h | 4 ++-- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c index d3f39e8..3e003fe 100644 --- a/drivers/net/ucc_geth.c +++ b/drivers/net/ucc_geth.c @@ -270,7 +270,7 @@ static int fill_init_enet_entries(struct ucc_geth_private *ugeth, u8 num_entries, u32 thread_size, u32 thread_alignment, - enum qe_risc_allocation risc, + unsigned int risc, int skip_page_for_first_entry) { u32 init_enet_offset; @@ -307,7 +307,7 @@ static int fill_init_enet_entries(struct ucc_geth_private *ugeth, static int return_init_enet_entries(struct ucc_geth_private *ugeth, u32 *p_start, u8 num_entries, - enum qe_risc_allocation risc, + unsigned int risc, int skip_page_for_first_entry) { u32 init_enet_offset; @@ -342,7 +342,7 @@ static int dump_init_enet_entries(struct ucc_geth_private *ugeth, u32 __iomem *p_start, u8 num_entries, u32 thread_size, - enum qe_risc_allocation risc, + unsigned int risc, int skip_page_for_first_entry) { u32 init_enet_offset; @@ -2134,6 +2134,14 @@ static int ucc_struct_init(struct ucc_geth_private *ugeth) return -ENOMEM; } + /* read the number of risc engines, update the riscTx and riscRx + * if there are 4 riscs in QE + */ + if (qe_get_num_of_risc() == 4) { + ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS; + ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS; + } + ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs)); if (!ugeth->ug_regs) { if (netif_msg_probe(ugeth)) diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h index 2f8ee7c..46bb1d2 100644 --- a/drivers/net/ucc_geth.h +++ b/drivers/net/ucc_geth.h @@ -1120,8 +1120,8 @@ struct ucc_geth_info { enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc; enum ucc_geth_num_of_threads numThreadsTx; enum ucc_geth_num_of_threads numThreadsRx; - enum qe_risc_allocation riscTx; - enum qe_risc_allocation riscRx; + unsigned int riscTx; + unsigned int riscRx; }; /* structure representing UCC GETH */