From patchwork Sun Aug 11 10:23:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?546L5a6H6Iiq?= X-Patchwork-Id: 266322 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from casper.infradead.org (unknown [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2B9C42C00CE for ; Sun, 11 Aug 2013 20:25:35 +1000 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V8Spy-0000sz-Vy; Sun, 11 Aug 2013 10:25:27 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V8Spx-0001Wd-Aw; Sun, 11 Aug 2013 10:25:25 +0000 Received: from mail-pd0-x233.google.com ([2607:f8b0:400e:c02::233]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V8Spv-0001WH-5P for linux-mtd@lists.infradead.org; Sun, 11 Aug 2013 10:25:24 +0000 Received: by mail-pd0-f179.google.com with SMTP id v10so2236674pde.24 for ; Sun, 11 Aug 2013 03:25:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=IMXsgVbmdyMUfpREwGv1Mp+M4aV+eul/PqV1m0nEBTU=; b=jlIfP8hAfZvqtskKVHzEUIylRrvVk1hVyPSCwd+OmiQRCJ1UdP4qRM9k58RgXJ3x8b 9oh+HIse5vXQZoolB4VWrlE5isfxCNiaSQvfURZwtdhg231+sG6W1g4VZ+xO3GzK9G61 mNfQHerM3e7UN9/cvzKbACiWpFuvBo0CcspOPwai1XPhYrVkOY/mDUd1yUSa/TCm5aJe M+8Q/UYULrONei7V0y7N1MJ9+bj8MshCC/Ka/zmbM4VmQnv4s8iaAVFP4fwjimENafto CDxCX6/HF2Vh5oRrgjIOwm/xOsZq8pVuCfIjFmtq19XFhpU/JCp9UoBSXqD+K3vdaxCv 6HPw== X-Received: by 10.68.233.134 with SMTP id tw6mr19669907pbc.9.1376216701154; Sun, 11 Aug 2013 03:25:01 -0700 (PDT) Received: from localhost.localdomain ([218.24.172.134]) by mx.google.com with ESMTPSA id il4sm30576719pbb.36.2013.08.11.03.24.58 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 11 Aug 2013 03:25:00 -0700 (PDT) From: wangyuhang To: broonie@kernel.org, sourav.poddar@ti.com, pekon@ti.com, tpiepho@gmail.com, spi-devel-general@lists.sourceforge.net, linux-mtd@lists.infradead.org Subject: [PATCH v3 2/2]spi: DUAL and QUAD support Date: Sun, 11 Aug 2013 18:23:50 +0800 Message-Id: <1376216630-5915-1-git-send-email-wangyuhang2014@gmail.com> X-Mailer: git-send-email 1.7.9.5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130811_062523_449681_5822F02A X-CRM114-Status: GOOD ( 14.70 ) X-Spam-Score: -1.8 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (wangyuhang2014[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (wangyuhang2014[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: wangyuhang2014@gmail.com X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org fix two things in previous patch 1. Change the value of transfer bit macro(SPI_NBITS_SINGLE, SPI_NBITS_DUAL SPI_NBITS_QUAD) to 0x01, 0x02 and 0x04 to match the actual wires in spidev.h. 2. To keep tx_nbits and rx_nbits in @spi_ioc_transfer compatible to existed binary in userspace, add SPI_SPIDEV_TRPBIT in Kconfig to make user select appropriate spi_ioc_transfer. Signed-off-by: wangyuhang --- drivers/spi/Kconfig | 10 ++++++++++ drivers/spi/spidev.c | 30 ++++++++++++++++++++++++++++++ include/uapi/linux/spi/spidev.h | 19 ++++++++++++++++++- 3 files changed, 58 insertions(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2be0de9..55ad87c 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -496,6 +496,16 @@ config SPI_SPIDEV Note that this application programming interface is EXPERIMENTAL and hence SUBJECT TO CHANGE WITHOUT NOTICE while it stabilizes. +config SPI_SPIDEV_TRPBIT + bool "Spidev support set transfer bit in user space" + depends on SPI_SPIDEV + default n + help + This supports user set transfer bit(SINGLE,DUAL,QUAD). + this will expand the struct spi_ioc_transfer with tx_nbits and + rx_nbits. Then you should set that with SPI_NBITS_SINGLE/ + SPI_NBITS_DUAL/SPI_NBITS_QUAD depend on your demand. + config SPI_TLE62X0 tristate "Infineon TLE62X0 (for power switching)" depends on SYSFS diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 2e0655d..33d7d24 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -75,6 +75,9 @@ static DECLARE_BITMAP(minors, N_SPI_MINORS); | SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP \ | SPI_NO_CS | SPI_READY) +#define SPI_EXTMODE_MASK (SPI_MODE_MASK | SPI_TX_DUAL \ + | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD) + struct spidev_data { dev_t devt; spinlock_t spi_lock; @@ -268,6 +271,10 @@ static int spidev_message(struct spidev_data *spidev, k_tmp->bits_per_word = u_tmp->bits_per_word; k_tmp->delay_usecs = u_tmp->delay_usecs; k_tmp->speed_hz = u_tmp->speed_hz; +#ifdef CONFIG_SPI_SPIDEV_TRPBIT + k_tmp->tx_nbits = u_tmp->tx_nbits; + k_tmp->rx_nbits = u_tmp->rx_nbits; +#endif #ifdef VERBOSE dev_dbg(&spidev->spi->dev, " xfer len %zd %s%s%s%dbits %u usec %uHz\n", @@ -369,6 +376,10 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) case SPI_IOC_RD_MAX_SPEED_HZ: retval = __put_user(spi->max_speed_hz, (__u32 __user *)arg); break; + case SPI_IOC_EXTRD_MODE: + retval = __put_user(spi->mode & SPI_EXTMODE_MASK, + (__u16 __user *)arg); + break; /* write requests */ case SPI_IOC_WR_MODE: @@ -433,6 +444,25 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) dev_dbg(&spi->dev, "%d Hz (max)\n", tmp); } break; + case SPI_IOC_EXTWR_MODE: + retval = __get_user(tmp, (u16 __user *)arg); + if (retval == 0) { + u16 save = spi->mode; + + if (tmp & ~SPI_EXTMODE_MASK) { + retval = -EINVAL; + break; + } + + tmp |= spi->mode & ~SPI_EXTMODE_MASK; + spi->mode = (u16)tmp; + retval = spi_setup(spi); + if (retval < 0) + spi->mode = save; + else + dev_dbg(&spi->dev, "spi mode %02x\n", tmp); + } + break; default: /* segmented and/or full-duplex I/O request */ diff --git a/include/uapi/linux/spi/spidev.h b/include/uapi/linux/spi/spidev.h index 52d9ed0..c3a0244 100644 --- a/include/uapi/linux/spi/spidev.h +++ b/include/uapi/linux/spi/spidev.h @@ -42,7 +42,14 @@ #define SPI_LOOP 0x20 #define SPI_NO_CS 0x40 #define SPI_READY 0x80 - +#define SPI_TX_DUAL 0x100 +#define SPI_TX_QUAD 0x200 +#define SPI_RX_DUAL 0x400 +#define SPI_RX_QUAD 0x800 + +#define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ +#define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ +#define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ /*---------------------------------------------------------------------------*/ /* IOCTL commands */ @@ -54,6 +61,8 @@ * @tx_buf: Holds pointer to userspace buffer with transmit data, or null. * If no data is provided, zeroes are shifted out. * @rx_buf: Holds pointer to userspace buffer for receive data, or null. + * @tx_nbits: number of bits used for writting. + * @rx_nbits: number of bits used for reading. * @len: Length of tx and rx buffers, in bytes. * @speed_hz: Temporary override of the device's bitrate. * @bits_per_word: Temporary override of the device's wordsize. @@ -86,6 +95,10 @@ struct spi_ioc_transfer { __u64 tx_buf; __u64 rx_buf; +#ifdef CONFIG_SPI_SPIDEV_TRPBIT + __u8 tx_nbits; + __u8 rx_nbits; +#endif __u32 len; __u32 speed_hz; @@ -126,6 +139,10 @@ struct spi_ioc_transfer { #define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, __u32) #define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, __u32) +/* Read / Write of SPI mode (including SPI DUAL/QUAD) */ +#define SPI_IOC_EXTRD_MODE _IOR(SPI_IOC_MAGIC, 5, __u16) +#define SPI_IOC_EXTWR_MODE _IOW(SPI_IOC_MAGIC, 5, __u16) + #endif /* SPIDEV_H */