From patchwork Fri Aug 9 15:03:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 266080 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 494B72C00A2 for ; Sat, 10 Aug 2013 01:10:40 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 15D694A021; Fri, 9 Aug 2013 17:10:39 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GVHhUw1hmsEc; Fri, 9 Aug 2013 17:10:38 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CA5934A027; Fri, 9 Aug 2013 17:10:37 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E47FE4A01E for ; Fri, 9 Aug 2013 17:10:31 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XHlvIsi+Qx3L for ; Fri, 9 Aug 2013 17:10:27 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ob0-f181.google.com (mail-ob0-f181.google.com [209.85.214.181]) by theia.denx.de (Postfix) with ESMTPS id 74A544A02D for ; Fri, 9 Aug 2013 17:10:11 +0200 (CEST) Received: by mail-ob0-f181.google.com with SMTP id dn14so6607150obc.12 for ; Fri, 09 Aug 2013 08:10:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+oEtGsuvpOAyY+oRDRcnQnd2nHL6peBBDkQLbyA+SjA=; b=eUYMjtVkT921Rh14XCEwjh++1B/ipppxq2vJPTsFiGWT77qNGeIQ/ETmwiTJiXxskf lypqEH5oL01MW/l1/dEvCna8Q/gWWUaHZLgobcngzP+In7uEEV4lzd+EmdPJyncd0SdZ +Qy5V5W4WcNh8Ie4mJFP8uT1nZuZNgnplpeCC+aa3taPo53SmRrhp+kfh4gH1oPF3gaU yqcloc1XGgvFzsCEX3HpBLxYJFHfDj23G4qeoTFJDn4NT4e97QFyqrYsG6cJqD6QzUcL b/XE3C3l3pMRQiCTZNd9Cc2sUJ305cql/SQBPCPw+9xOzAnJj1dM4/RbZD1xSurBhDLW 6c4Q== X-Gm-Message-State: ALoCoQnsul4y3Lw08sC09uhpNfibrTXwMtrwxuau0R930Ux8NZDEtSDlWSFw2KRcP82qxOVbh3mi X-Received: by 10.60.174.77 with SMTP id bq13mr783395oec.35.1376060669762; Fri, 09 Aug 2013 08:04:29 -0700 (PDT) Received: from slackpad.drs.calxeda.com (f053081188.adsl.alicedsl.de. [78.53.81.188]) by mx.google.com with ESMTPSA id hm1sm19249781obb.9.2013.08.09.08.04.26 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 09 Aug 2013 08:04:29 -0700 (PDT) From: Andre Przywara To: trini@ti.com, albert.u.boot@aribaud.net, christoffer.dall@linaro.org Date: Fri, 9 Aug 2013 17:03:06 +0200 Message-Id: <1376060592-10824-3-git-send-email-andre.przywara@linaro.org> X-Mailer: git-send-email 1.7.12.1 In-Reply-To: <1376060592-10824-1-git-send-email-andre.przywara@linaro.org> References: <1376060592-10824-1-git-send-email-andre.przywara@linaro.org> Cc: peter.maydell@linaro.org, geoff.levand@linaro.org, patches@linaro.org, marc.zyngier@arm.com, agraf@suse.de, u-boot@lists.denx.de, nicknickolaev@gmail.com, kvmarm@lists.cs.columbia.edu Subject: [U-Boot] [PATCH v4 2/8] ARM: add secure monitor handler to switch to non-secure state X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de A prerequisite for using virtualization is to be in HYP mode, which requires the CPU to be in non-secure state first. Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine which switches the CPU to non-secure state by setting the NS and associated bits. According to the ARM architecture reference manual this should not be done in SVC mode, so we have to setup a SMC handler for this. We create a new vector table to avoid interference with other boards. The MVBAR register will be programmed later just before the smc call. Signed-off-by: Andre Przywara --- arch/arm/cpu/armv7/Makefile | 4 +++ arch/arm/cpu/armv7/nonsec_virt.S | 55 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 arch/arm/cpu/armv7/nonsec_virt.S diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 7a8c2d0..11a8ad5 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -36,6 +36,10 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONF SOBJS += lowlevel_init.o endif +ifneq ($(CONFIG_ARMV7_NONSEC),) +SOBJS += nonsec_virt.o +endif + SRCS := $(START:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S new file mode 100644 index 0000000..dbe5c0f --- /dev/null +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -0,0 +1,55 @@ +/* + * code for switching cores into non-secure state + * + * Copyright (c) 2013 Andre Przywara + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* the vector table for secure state */ +_monitor_vectors: + .word 0 /* reset */ + .word 0 /* undef */ + adr pc, _secure_monitor + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 /* pad */ + +/* + * secure monitor handler + * U-boot calls this "software interrupt" in start.S + * This is executed on a "smc" instruction, we use a "smc #0" to switch + * to non-secure state. + * We use only r0 and r1 here, due to constraints in the caller. + */ + .align 5 +_secure_monitor: + mrc p15, 0, r1, c1, c1, 0 @ read SCR + bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits + orr r1, r1, #0x31 @ enable NS, AW, FW bits + + mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) + + movs pc, lr @ return to non-secure SVC +