From patchwork Thu Aug 8 14:40:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 265748 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 44B332C008E for ; Fri, 9 Aug 2013 00:41:23 +1000 (EST) Received: from localhost ([::1]:48695 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7ROy-0007KM-27 for incoming@patchwork.ozlabs.org; Thu, 08 Aug 2013 10:41:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38138) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7ROW-0007GX-IF for qemu-devel@nongnu.org; Thu, 08 Aug 2013 10:40:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V7ROM-0001KS-S6 for qemu-devel@nongnu.org; Thu, 08 Aug 2013 10:40:52 -0400 Received: from multi.imgtec.com ([194.200.65.239]:50037) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7ROM-0001Jr-Dk for qemu-devel@nongnu.org; Thu, 08 Aug 2013 10:40:42 -0400 From: James Hogan To: , Aurelien Jarno Date: Thu, 8 Aug 2013 15:40:23 +0100 Message-ID: <1375972823-25333-1-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 1.8.1.2 MIME-Version: 1.0 X-Originating-IP: [192.168.154.65] X-SEF-Processed: 7_3_0_01192__2013_08_08_15_40_41 X-detected-operating-system: by eggs.gnu.org: Windows XP X-Received-From: 194.200.65.239 Cc: James Hogan , Richard Henderson Subject: [Qemu-devel] [PATCH] tcg/mips: fix invalid op definition errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org tcg/mips/tcg-target.h defines various operations conditionally depending upon the isa revision, however these operations are included in mips_op_defs[] unconditionally resulting in the following runtime errors if CONFIG_DEBUG_TCG is defined: Invalid op definition for movcond_i32 Invalid op definition for rotl_i32 Invalid op definition for rotr_i32 Invalid op definition for deposit_i32 Invalid op definition for bswap16_i32 Invalid op definition for bswap32_i32 tcg/tcg.c:1196: tcg fatal error Fix with ifdefs like the i386 backend does for movcond_i32. Signed-off-by: James Hogan Cc: Aurelien Jarno Cc: Richard Henderson Reviewed-by: Richard Henderson --- tcg/mips/tcg-target.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 373c364..793532e 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -1617,19 +1617,29 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_shl_i32, { "r", "rZ", "ri" } }, { INDEX_op_shr_i32, { "r", "rZ", "ri" } }, { INDEX_op_sar_i32, { "r", "rZ", "ri" } }, +#if TCG_TARGET_HAS_rot_i32 { INDEX_op_rotr_i32, { "r", "rZ", "ri" } }, { INDEX_op_rotl_i32, { "r", "rZ", "ri" } }, +#endif +#if TCG_TARGET_HAS_bswap16_i32 { INDEX_op_bswap16_i32, { "r", "r" } }, +#endif +#if TCG_TARGET_HAS_bswap32_i32 { INDEX_op_bswap32_i32, { "r", "r" } }, +#endif { INDEX_op_ext8s_i32, { "r", "rZ" } }, { INDEX_op_ext16s_i32, { "r", "rZ" } }, +#if TCG_TARGET_HAS_deposit_i32 { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, +#endif { INDEX_op_brcond_i32, { "rZ", "rZ" } }, +#if TCG_TARGET_HAS_movcond_i32 { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } }, +#endif { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },