From patchwork Thu Aug 8 00:30:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 265623 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id E228B2C0114 for ; Thu, 8 Aug 2013 10:31:04 +1000 (EST) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe003.messaging.microsoft.com [216.32.181.183]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "MSIT Machine Auth CA 2" (not verified)) by ozlabs.org (Postfix) with ESMTPS id E5F7A2C009E for ; Thu, 8 Aug 2013 10:30:32 +1000 (EST) Received: from mail56-ch1-R.bigfish.com (10.43.68.230) by CH1EHSOBE013.bigfish.com (10.43.70.63) with Microsoft SMTP Server id 14.1.225.22; Thu, 8 Aug 2013 00:30:26 +0000 Received: from mail56-ch1 (localhost [127.0.0.1]) by mail56-ch1-R.bigfish.com (Postfix) with ESMTP id BD12E3000E5 for ; Thu, 8 Aug 2013 00:30:26 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 1 X-BigFish: VS1(z37d5kz98dI1432Izz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2dh2a8h668h839h944hd25hf0ah1220h1288h12a5h12a9h12bdh137ah13b6h1441h14ddh1504h1537h153bh162dh1631h1758h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1155h) Received: from mail56-ch1 (localhost.localdomain [127.0.0.1]) by mail56-ch1 (MessageSwitch) id 1375921825234350_7605; Thu, 8 Aug 2013 00:30:25 +0000 (UTC) Received: from CH1EHSMHS023.bigfish.com (snatpool3.int.messaging.microsoft.com [10.43.68.228]) by mail56-ch1.bigfish.com (Postfix) with ESMTP id 34CB318004C for ; Thu, 8 Aug 2013 00:30:25 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS023.bigfish.com (10.43.70.23) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 8 Aug 2013 00:30:24 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.3.136.1; Thu, 8 Aug 2013 00:30:24 +0000 Received: from home.buserror.net ([10.214.83.234]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r780ULvL032730; Wed, 7 Aug 2013 17:30:22 -0700 Date: Wed, 7 Aug 2013 19:30:21 -0500 From: Scott Wood To: Minghuan Lian Subject: Re: [1/3,v2] powerpc/dts: update MSI bindings doc for MPIC v4.3 Message-ID: <20130808003021.GA22932@home.buserror.net> References: <1371812354-1962-1-git-send-email-Minghuan.Lian@freescale.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1371812354-1962-1-git-send-email-Minghuan.Lian@freescale.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: linuxppc-dev@lists.ozlabs.org, Zang Roy-R61911 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Fri, Jun 21, 2013 at 06:59:12PM +0800, Minghuan Lian wrote: > Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains > MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports > 16 MSI registers, but uses different IBS and SRS shift. When using > MSIR1, the interrupt number is not consecutive. It is hard to use > 'msi-available-ranges' to describe the ranges of the available > interrupt, so MPIC v4.3 does not support this property. > > Signed-off-by: Minghuan Lian > > --- > v2 log: > 1. move msi-available-ranges to optional properties. > > .../devicetree/bindings/powerpc/fsl/msi-pic.txt | 51 +++++++++++++++++----- > 1 file changed, 40 insertions(+), 11 deletions(-) Applied with these changes: -Scott diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt index d82b080..82dd5b6 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt @@ -1,13 +1,13 @@ * Freescale MSI interrupt controller Required properties: -- compatible : compatible list, may contains one or two entries, - first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572, +- compatible : compatible list, may contain one or two entries + The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572, etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is - provided to access these 16 registers, compatible "fsl,mpic-msi-v4.3" - should be used. The first entry is optional, the second entry must be + provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3" + should be used. The first entry is optional; the second entry is required. - reg : It may contain one or two regions. The first region should contain